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[89.104.8.249]) by smtp.gmail.com with ESMTPSA id u2-20020a17090617c200b0098ce63e36e9sm4138253eje.16.2023.10.21.13.05.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Oct 2023 13:05:44 -0700 (PDT) From: Phil Dennis-Jordan To: qemu-devel@nongnu.org Cc: dirty@apple.com, roman@roolebo.dev, pbonzini@redhat.com, lists@philjordan.eu, phil@philjordan.eu Subject: [PATCH v2 1/4] i386: hvf: Adds support for INVTSC cpuid bit Date: Sat, 21 Oct 2023 22:05:15 +0200 Message-Id: <20231021200518.30125-2-phil@philjordan.eu> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20231021200518.30125-1-phil@philjordan.eu> References: <20231021200518.30125-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::533; envelope-from=phil@philjordan.eu; helo=mail-ed1-x533.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch adds the INVTSC bit to the Hypervisor.framework accelerator's CPUID bit passthrough allow-list. Previously, specifying +invtsc in the CPU configuration would fail with the following warning despite the host CPU advertising the feature: qemu-system-x86_64: warning: host doesn't support requested feature: CPUID.80000007H:EDX.invtsc [bit 8] x86 macOS itself relies on a fixed rate TSC for its own Mach absolute time timestamp mechanism, so there's no reason we can't enable this bit for guests. When the feature is enabled, a migration blocker is installed. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov --- target/i386/hvf/hvf.c | 18 ++++++++++++++++++ target/i386/hvf/x86_cpuid.c | 4 ++++ 2 files changed, 22 insertions(+) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index cb2cd0b02f..43d64574ad 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -49,6 +49,8 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/memalign.h" +#include "qapi/error.h" +#include "migration/blocker.h" #include "sysemu/hvf.h" #include "sysemu/hvf_int.h" @@ -74,6 +76,8 @@ #include "qemu/accel.h" #include "target/i386/cpu.h" +static Error *invtsc_mig_blocker; + void vmx_update_tpr(CPUState *cpu) { /* TODO: need integrate APIC handling */ @@ -221,6 +225,8 @@ int hvf_arch_init_vcpu(CPUState *cpu) { X86CPU *x86cpu = X86_CPU(cpu); CPUX86State *env = &x86cpu->env; + Error *local_err = NULL; + int r; uint64_t reqCap; init_emu(); @@ -238,6 +244,18 @@ int hvf_arch_init_vcpu(CPUState *cpu) } } + if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) && + invtsc_mig_blocker == NULL) { + error_setg(&invtsc_mig_blocker, + "State blocked by non-migratable CPU device (invtsc flag)"); + r = migrate_add_blocker(&invtsc_mig_blocker, &local_err); + if (r < 0) { + error_report_err(local_err); + return r; + } + } + + if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &hvf_state->hvf_caps->vmx_cap_pinbased)) { abort(); diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c index 9380b90496..e56cd8411b 100644 --- a/target/i386/hvf/x86_cpuid.c +++ b/target/i386/hvf/x86_cpuid.c @@ -146,6 +146,10 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_OSVW | CPUID_EXT3_XOP | CPUID_EXT3_FMA4 | CPUID_EXT3_TBM; break; + case 0x80000007: + edx &= CPUID_APM_INVTSC; + eax = ebx = ecx = 0; + break; default: return 0; }