diff mbox series

[v4,09/13] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT

Message ID 20231025200713.580814-10-sunilvl@ventanamicro.com (mailing list archive)
State New, archived
Headers show
Series RISC-V: ACPI: Enable AIA, PLIC and update RHCT | expand

Commit Message

Sunil V L Oct. 25, 2023, 8:07 p.m. UTC 
MMU type information is available via MMU node in RHCT. Add this node in
RHCT.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 hw/riscv/virt-acpi-build.c | 37 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

Comments

Andrew Jones Oct. 26, 2023, 8:31 a.m. UTC | #1 
On Thu, Oct 26, 2023 at 01:37:09AM +0530, Sunil V L wrote:
> MMU type information is available via MMU node in RHCT. Add this node in
> RHCT.
> 
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>  hw/riscv/virt-acpi-build.c | 37 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 36 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index ebe7062b9b..dc7c0213f5 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -159,6 +159,8 @@ static void build_rhct(GArray *table_data,
>      size_t len, aligned_len;
>      uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
>      RISCVCPU *cpu = &s->soc[0].harts[0];
> +    uint32_t mmu_offset = 0;
> +    uint8_t satp_mode_max;
>      char *isa;
>  
>      AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
> @@ -178,6 +180,10 @@ static void build_rhct(GArray *table_data,
>          num_rhct_nodes++;
>      }
>  
> +    if (cpu->cfg.satp_mode.supported != 0) {
> +        num_rhct_nodes++;
> +    }
> +
>      /* Number of RHCT nodes*/
>      build_append_int_noprefix(table_data, num_rhct_nodes, 4);
>  
> @@ -233,6 +239,26 @@ static void build_rhct(GArray *table_data,
>          }
>      }
>  
> +    /* MMU node structure */
> +    if (cpu->cfg.satp_mode.supported != 0) {
> +        satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
> +        mmu_offset = table_data->len - table.table_offset;
> +        build_append_int_noprefix(table_data, 2, 2);    /* Type */
> +        build_append_int_noprefix(table_data, 8, 2);    /* Length */
> +        build_append_int_noprefix(table_data, 0x1, 2);  /* Revision */
> +        build_append_int_noprefix(table_data, 0, 1);    /* Reserved */
> +        /* MMU Type */
> +        if (satp_mode_max == VM_1_10_SV57) {
> +            build_append_int_noprefix(table_data, 2, 1);    /* Sv57 */
> +        } else if (satp_mode_max == VM_1_10_SV48) {
> +            build_append_int_noprefix(table_data, 1, 1);    /* Sv48 */
> +        } else if (satp_mode_max == VM_1_10_SV39) {
> +            build_append_int_noprefix(table_data, 0, 1);    /* Sv39 */
> +        } else {
> +            assert(1);
> +        }
> +    }
> +
>      /* Hart Info Node */
>      for (int i = 0; i < arch_ids->len; i++) {
>          len = 16;
> @@ -245,17 +271,26 @@ static void build_rhct(GArray *table_data,
>              num_offsets++;
>          }
>  
> +        if (mmu_offset) {
> +            len += 4;
> +            num_offsets++;
> +        }
> +
>          build_append_int_noprefix(table_data, len, 2);
>          build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
>          /* Number of offsets */
>          build_append_int_noprefix(table_data, num_offsets, 2);
>          build_append_int_noprefix(table_data, i, 4);   /* ACPI Processor UID */
> -
>          /* Offsets */
>          build_append_int_noprefix(table_data, isa_offset, 4);
> +        if (mmu_offset) {
> +            build_append_int_noprefix(table_data, mmu_offset, 4);
> +        }
> +

In the previous version of this patch the MMU node was getting generated
above the CMO node, so its offset was less than those of the CMO node,
and why I recommended moving it up here. But, in this version, the MMU
node is now getting generated after the CMO node, so moving this up
means the offsets are still not in ascending order.

>          if (cmo_offset) {
>              build_append_int_noprefix(table_data, cmo_offset, 4);
>          }
> +
>      }
>  
>      acpi_table_end(linker, &table);
> -- 
> 2.39.2
> 
>

Anyway,

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Thanks,
drew
Sunil V L Oct. 26, 2023, 12:33 p.m. UTC | #2 
On Thu, Oct 26, 2023 at 10:31:51AM +0200, Andrew Jones wrote:
> On Thu, Oct 26, 2023 at 01:37:09AM +0530, Sunil V L wrote:
> > MMU type information is available via MMU node in RHCT. Add this node in
> > RHCT.
> > 
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> > ---
> >  hw/riscv/virt-acpi-build.c | 37 ++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 36 insertions(+), 1 deletion(-)
> > 
> > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> > index ebe7062b9b..dc7c0213f5 100644
> > --- a/hw/riscv/virt-acpi-build.c
> > +++ b/hw/riscv/virt-acpi-build.c
> > @@ -159,6 +159,8 @@ static void build_rhct(GArray *table_data,
> >      size_t len, aligned_len;
> >      uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
> >      RISCVCPU *cpu = &s->soc[0].harts[0];
> > +    uint32_t mmu_offset = 0;
> > +    uint8_t satp_mode_max;
> >      char *isa;
> >  
> >      AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
> > @@ -178,6 +180,10 @@ static void build_rhct(GArray *table_data,
> >          num_rhct_nodes++;
> >      }
> >  
> > +    if (cpu->cfg.satp_mode.supported != 0) {
> > +        num_rhct_nodes++;
> > +    }
> > +
> >      /* Number of RHCT nodes*/
> >      build_append_int_noprefix(table_data, num_rhct_nodes, 4);
> >  
> > @@ -233,6 +239,26 @@ static void build_rhct(GArray *table_data,
> >          }
> >      }
> >  
> > +    /* MMU node structure */
> > +    if (cpu->cfg.satp_mode.supported != 0) {
> > +        satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
> > +        mmu_offset = table_data->len - table.table_offset;
> > +        build_append_int_noprefix(table_data, 2, 2);    /* Type */
> > +        build_append_int_noprefix(table_data, 8, 2);    /* Length */
> > +        build_append_int_noprefix(table_data, 0x1, 2);  /* Revision */
> > +        build_append_int_noprefix(table_data, 0, 1);    /* Reserved */
> > +        /* MMU Type */
> > +        if (satp_mode_max == VM_1_10_SV57) {
> > +            build_append_int_noprefix(table_data, 2, 1);    /* Sv57 */
> > +        } else if (satp_mode_max == VM_1_10_SV48) {
> > +            build_append_int_noprefix(table_data, 1, 1);    /* Sv48 */
> > +        } else if (satp_mode_max == VM_1_10_SV39) {
> > +            build_append_int_noprefix(table_data, 0, 1);    /* Sv39 */
> > +        } else {
> > +            assert(1);
> > +        }
> > +    }
> > +
> >      /* Hart Info Node */
> >      for (int i = 0; i < arch_ids->len; i++) {
> >          len = 16;
> > @@ -245,17 +271,26 @@ static void build_rhct(GArray *table_data,
> >              num_offsets++;
> >          }
> >  
> > +        if (mmu_offset) {
> > +            len += 4;
> > +            num_offsets++;
> > +        }
> > +
> >          build_append_int_noprefix(table_data, len, 2);
> >          build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> >          /* Number of offsets */
> >          build_append_int_noprefix(table_data, num_offsets, 2);
> >          build_append_int_noprefix(table_data, i, 4);   /* ACPI Processor UID */
> > -
> >          /* Offsets */
> >          build_append_int_noprefix(table_data, isa_offset, 4);
> > +        if (mmu_offset) {
> > +            build_append_int_noprefix(table_data, mmu_offset, 4);
> > +        }
> > +
> 
> In the previous version of this patch the MMU node was getting generated
> above the CMO node, so its offset was less than those of the CMO node,
> and why I recommended moving it up here. But, in this version, the MMU
> node is now getting generated after the CMO node, so moving this up
> means the offsets are still not in ascending order.
> 
Yeah, after changing here I realized MMU node type is logically better
to be created after cmo. So, I changed the creation order but forgot
reorder here. Will update in the next revision.

Thanks,
Sunil
diff mbox series

Patch

diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index ebe7062b9b..dc7c0213f5 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -159,6 +159,8 @@  static void build_rhct(GArray *table_data,
     size_t len, aligned_len;
     uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
     RISCVCPU *cpu = &s->soc[0].harts[0];
+    uint32_t mmu_offset = 0;
+    uint8_t satp_mode_max;
     char *isa;
 
     AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -178,6 +180,10 @@  static void build_rhct(GArray *table_data,
         num_rhct_nodes++;
     }
 
+    if (cpu->cfg.satp_mode.supported != 0) {
+        num_rhct_nodes++;
+    }
+
     /* Number of RHCT nodes*/
     build_append_int_noprefix(table_data, num_rhct_nodes, 4);
 
@@ -233,6 +239,26 @@  static void build_rhct(GArray *table_data,
         }
     }
 
+    /* MMU node structure */
+    if (cpu->cfg.satp_mode.supported != 0) {
+        satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+        mmu_offset = table_data->len - table.table_offset;
+        build_append_int_noprefix(table_data, 2, 2);    /* Type */
+        build_append_int_noprefix(table_data, 8, 2);    /* Length */
+        build_append_int_noprefix(table_data, 0x1, 2);  /* Revision */
+        build_append_int_noprefix(table_data, 0, 1);    /* Reserved */
+        /* MMU Type */
+        if (satp_mode_max == VM_1_10_SV57) {
+            build_append_int_noprefix(table_data, 2, 1);    /* Sv57 */
+        } else if (satp_mode_max == VM_1_10_SV48) {
+            build_append_int_noprefix(table_data, 1, 1);    /* Sv48 */
+        } else if (satp_mode_max == VM_1_10_SV39) {
+            build_append_int_noprefix(table_data, 0, 1);    /* Sv39 */
+        } else {
+            assert(1);
+        }
+    }
+
     /* Hart Info Node */
     for (int i = 0; i < arch_ids->len; i++) {
         len = 16;
@@ -245,17 +271,26 @@  static void build_rhct(GArray *table_data,
             num_offsets++;
         }
 
+        if (mmu_offset) {
+            len += 4;
+            num_offsets++;
+        }
+
         build_append_int_noprefix(table_data, len, 2);
         build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
         /* Number of offsets */
         build_append_int_noprefix(table_data, num_offsets, 2);
         build_append_int_noprefix(table_data, i, 4);   /* ACPI Processor UID */
-
         /* Offsets */
         build_append_int_noprefix(table_data, isa_offset, 4);
+        if (mmu_offset) {
+            build_append_int_noprefix(table_data, mmu_offset, 4);
+        }
+
         if (cmo_offset) {
             build_append_int_noprefix(table_data, cmo_offset, 4);
         }
+
     }
 
     acpi_table_end(linker, &table);