| Message ID | 20231025200713.580814-6-sunilvl@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V: ACPI: Enable AIA, PLIC and update RHCT | expand |
On Thu, Oct 26, 2023 at 01:37:05AM +0530, Sunil V L wrote: > Update the RINTC structure in MADT with AIA related fields. > > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Acked-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/riscv/virt-acpi-build.c | 66 +++++++++++++++++++++++++++++++++++--- > 1 file changed, 62 insertions(+), 4 deletions(-) > > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c > index d8772c2821..073c85f327 100644 > --- a/hw/riscv/virt-acpi-build.c > +++ b/hw/riscv/virt-acpi-build.c > @@ -38,6 +38,7 @@ > #include "hw/intc/riscv_aclint.h" > > #define ACPI_BUILD_TABLE_SIZE 0x20000 > +#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) > > typedef struct AcpiBuildState { > /* Copy of table in RAM (for patching) */ > @@ -58,18 +59,42 @@ static void acpi_align_size(GArray *blob, unsigned align) > } > > static void riscv_acpi_madt_add_rintc(uint32_t uid, > + uint32_t local_cpu_id, > const CPUArchIdList *arch_ids, > - GArray *entry) > + GArray *entry, > + RISCVVirtAIAType aia_type, > + uint64_t imsic_addr, > + uint32_t imsic_size) > { > uint64_t hart_id = arch_ids->cpus[uid].arch_id; > > build_append_int_noprefix(entry, 0x18, 1); /* Type */ > - build_append_int_noprefix(entry, 20, 1); /* Length */ > + build_append_int_noprefix(entry, 36, 1); /* Length */ > build_append_int_noprefix(entry, 1, 1); /* Version */ > build_append_int_noprefix(entry, 0, 1); /* Reserved */ > build_append_int_noprefix(entry, 0x1, 4); /* Flags */ > build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */ > build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */ > + /* External Interrupt Controller ID */ > + if (aia_type == VIRT_AIA_TYPE_APLIC) { > + build_append_int_noprefix(entry, > + ACPI_BUILD_INTC_ID( > + arch_ids->cpus[uid].props.node_id, > + local_cpu_id), > + 4); > + } else { > + build_append_int_noprefix(entry, 0, 4); > + } > + > + if (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { > + /* IMSIC Base address */ > + build_append_int_noprefix(entry, imsic_addr, 8); > + /* IMSIC Size */ > + build_append_int_noprefix(entry, imsic_size, 4); > + } else { > + build_append_int_noprefix(entry, 0, 8); > + build_append_int_noprefix(entry, 0, 4); > + } > } > > static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) > @@ -77,6 +102,11 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) > MachineClass *mc = MACHINE_GET_CLASS(s); > MachineState *ms = MACHINE(s); > const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); > + uint64_t imsic_socket_addr, imsic_addr; > + uint8_t guest_index_bits; > + uint32_t imsic_size, local_cpu_id, socket_id; > + > + guest_index_bits = imsic_num_bits(s->aia_guests + 1); > > for (int i = 0; i < arch_ids->len; i++) { > Aml *dev; > @@ -87,8 +117,19 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) > aml_append(dev, aml_name_decl("_UID", > aml_int(arch_ids->cpus[i].arch_id))); > > + socket_id = arch_ids->cpus[i].props.node_id; > + local_cpu_id = (arch_ids->cpus[i].arch_id - > + riscv_socket_first_hartid(ms, socket_id)) % > + riscv_socket_hart_count(ms, socket_id); > /* build _MAT object */ > - riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf); > + imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + > + (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); > + imsic_addr = imsic_socket_addr + > + local_cpu_id * IMSIC_HART_SIZE(guest_index_bits); > + imsic_size = IMSIC_HART_SIZE(guest_index_bits); > + > + riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, madt_buf, > + s->aia_type, imsic_addr, imsic_size); > aml_append(dev, aml_name_decl("_MAT", > aml_buffer(madt_buf->len, > (uint8_t *)madt_buf->data))); > @@ -227,6 +268,7 @@ static void build_dsdt(GArray *table_data, > * 5.2.12 Multiple APIC Description Table (MADT) > * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15 > * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view > + * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view > */ > static void build_madt(GArray *table_data, > BIOSLinker *linker, > @@ -235,6 +277,12 @@ static void build_madt(GArray *table_data, > MachineClass *mc = MACHINE_GET_CLASS(s); > MachineState *ms = MACHINE(s); > const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); > + uint64_t imsic_socket_addr, imsic_addr; > + uint8_t guest_index_bits; > + uint32_t imsic_size; > + uint32_t local_cpu_id, socket_id; > + > + guest_index_bits = imsic_num_bits(s->aia_guests + 1); > > AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id, > .oem_table_id = s->oem_table_id }; > @@ -246,7 +294,17 @@ static void build_madt(GArray *table_data, > > /* RISC-V Local INTC structures per HART */ > for (int i = 0; i < arch_ids->len; i++) { > - riscv_acpi_madt_add_rintc(i, arch_ids, table_data); > + socket_id = arch_ids->cpus[i].props.node_id; > + local_cpu_id = (arch_ids->cpus[i].arch_id - > + riscv_socket_first_hartid(ms, socket_id)) % > + riscv_socket_hart_count(ms, socket_id); > + imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + > + (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); > + imsic_addr = imsic_socket_addr + > + local_cpu_id * IMSIC_HART_SIZE(guest_index_bits); > + imsic_size = IMSIC_HART_SIZE(guest_index_bits); > + riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, table_data, > + s->aia_type, imsic_addr, imsic_size); All the above new lines identically match the new lines in acpi_dsdt_add_cpus(), so I suggest creating a helper function rather than duplicating them. > } > > acpi_table_end(linker, &table); > -- > 2.39.2 > > Otherwise, Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Thanks, drew
On Thu, Oct 26, 2023 at 10:46:56AM +0200, Andrew Jones wrote: > On Thu, Oct 26, 2023 at 01:37:05AM +0530, Sunil V L wrote: > > Update the RINTC structure in MADT with AIA related fields. > > > > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> > > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > > Acked-by: Alistair Francis <alistair.francis@wdc.com> > > --- > > hw/riscv/virt-acpi-build.c | 66 +++++++++++++++++++++++++++++++++++--- > > 1 file changed, 62 insertions(+), 4 deletions(-) > > > > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c > > index d8772c2821..073c85f327 100644 > > --- a/hw/riscv/virt-acpi-build.c > > +++ b/hw/riscv/virt-acpi-build.c > > @@ -38,6 +38,7 @@ > > #include "hw/intc/riscv_aclint.h" > > > > #define ACPI_BUILD_TABLE_SIZE 0x20000 > > +#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) > > > > typedef struct AcpiBuildState { > > /* Copy of table in RAM (for patching) */ > > @@ -58,18 +59,42 @@ static void acpi_align_size(GArray *blob, unsigned align) > > } > > > > static void riscv_acpi_madt_add_rintc(uint32_t uid, > > + uint32_t local_cpu_id, > > const CPUArchIdList *arch_ids, > > - GArray *entry) > > + GArray *entry, > > + RISCVVirtAIAType aia_type, > > + uint64_t imsic_addr, > > + uint32_t imsic_size) > > { > > uint64_t hart_id = arch_ids->cpus[uid].arch_id; > > > > build_append_int_noprefix(entry, 0x18, 1); /* Type */ > > - build_append_int_noprefix(entry, 20, 1); /* Length */ > > + build_append_int_noprefix(entry, 36, 1); /* Length */ > > build_append_int_noprefix(entry, 1, 1); /* Version */ > > build_append_int_noprefix(entry, 0, 1); /* Reserved */ > > build_append_int_noprefix(entry, 0x1, 4); /* Flags */ > > build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */ > > build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */ > > + /* External Interrupt Controller ID */ > > + if (aia_type == VIRT_AIA_TYPE_APLIC) { > > + build_append_int_noprefix(entry, > > + ACPI_BUILD_INTC_ID( > > + arch_ids->cpus[uid].props.node_id, > > + local_cpu_id), > > + 4); > > + } else { > > + build_append_int_noprefix(entry, 0, 4); > > + } > > + > > + if (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { > > + /* IMSIC Base address */ > > + build_append_int_noprefix(entry, imsic_addr, 8); > > + /* IMSIC Size */ > > + build_append_int_noprefix(entry, imsic_size, 4); > > + } else { > > + build_append_int_noprefix(entry, 0, 8); > > + build_append_int_noprefix(entry, 0, 4); > > + } > > } > > > > static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) > > @@ -77,6 +102,11 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) > > MachineClass *mc = MACHINE_GET_CLASS(s); > > MachineState *ms = MACHINE(s); > > const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); > > + uint64_t imsic_socket_addr, imsic_addr; > > + uint8_t guest_index_bits; > > + uint32_t imsic_size, local_cpu_id, socket_id; > > + > > + guest_index_bits = imsic_num_bits(s->aia_guests + 1); > > > > for (int i = 0; i < arch_ids->len; i++) { > > Aml *dev; > > @@ -87,8 +117,19 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) > > aml_append(dev, aml_name_decl("_UID", > > aml_int(arch_ids->cpus[i].arch_id))); > > > > + socket_id = arch_ids->cpus[i].props.node_id; > > + local_cpu_id = (arch_ids->cpus[i].arch_id - > > + riscv_socket_first_hartid(ms, socket_id)) % > > + riscv_socket_hart_count(ms, socket_id); > > /* build _MAT object */ > > - riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf); > > + imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + > > + (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); > > + imsic_addr = imsic_socket_addr + > > + local_cpu_id * IMSIC_HART_SIZE(guest_index_bits); > > + imsic_size = IMSIC_HART_SIZE(guest_index_bits); > > + > > + riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, madt_buf, > > + s->aia_type, imsic_addr, imsic_size); > > aml_append(dev, aml_name_decl("_MAT", > > aml_buffer(madt_buf->len, > > (uint8_t *)madt_buf->data))); > > @@ -227,6 +268,7 @@ static void build_dsdt(GArray *table_data, > > * 5.2.12 Multiple APIC Description Table (MADT) > > * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15 > > * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view > > + * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view > > */ > > static void build_madt(GArray *table_data, > > BIOSLinker *linker, > > @@ -235,6 +277,12 @@ static void build_madt(GArray *table_data, > > MachineClass *mc = MACHINE_GET_CLASS(s); > > MachineState *ms = MACHINE(s); > > const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); > > + uint64_t imsic_socket_addr, imsic_addr; > > + uint8_t guest_index_bits; > > + uint32_t imsic_size; > > + uint32_t local_cpu_id, socket_id; > > + > > + guest_index_bits = imsic_num_bits(s->aia_guests + 1); > > > > AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id, > > .oem_table_id = s->oem_table_id }; > > @@ -246,7 +294,17 @@ static void build_madt(GArray *table_data, > > > > /* RISC-V Local INTC structures per HART */ > > for (int i = 0; i < arch_ids->len; i++) { > > - riscv_acpi_madt_add_rintc(i, arch_ids, table_data); > > + socket_id = arch_ids->cpus[i].props.node_id; > > + local_cpu_id = (arch_ids->cpus[i].arch_id - > > + riscv_socket_first_hartid(ms, socket_id)) % > > + riscv_socket_hart_count(ms, socket_id); > > + imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + > > + (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); > > + imsic_addr = imsic_socket_addr + > > + local_cpu_id * IMSIC_HART_SIZE(guest_index_bits); > > + imsic_size = IMSIC_HART_SIZE(guest_index_bits); > > + riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, table_data, > > + s->aia_type, imsic_addr, imsic_size); > > All the above new lines identically match the new lines in > acpi_dsdt_add_cpus(), so I suggest creating a helper function rather > than duplicating them. > Makes sense. Let me update in next revision. Thanks, Sunil
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index d8772c2821..073c85f327 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -38,6 +38,7 @@ #include "hw/intc/riscv_aclint.h" #define ACPI_BUILD_TABLE_SIZE 0x20000 +#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) typedef struct AcpiBuildState { /* Copy of table in RAM (for patching) */ @@ -58,18 +59,42 @@ static void acpi_align_size(GArray *blob, unsigned align) } static void riscv_acpi_madt_add_rintc(uint32_t uid, + uint32_t local_cpu_id, const CPUArchIdList *arch_ids, - GArray *entry) + GArray *entry, + RISCVVirtAIAType aia_type, + uint64_t imsic_addr, + uint32_t imsic_size) { uint64_t hart_id = arch_ids->cpus[uid].arch_id; build_append_int_noprefix(entry, 0x18, 1); /* Type */ - build_append_int_noprefix(entry, 20, 1); /* Length */ + build_append_int_noprefix(entry, 36, 1); /* Length */ build_append_int_noprefix(entry, 1, 1); /* Version */ build_append_int_noprefix(entry, 0, 1); /* Reserved */ build_append_int_noprefix(entry, 0x1, 4); /* Flags */ build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */ build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */ + /* External Interrupt Controller ID */ + if (aia_type == VIRT_AIA_TYPE_APLIC) { + build_append_int_noprefix(entry, + ACPI_BUILD_INTC_ID( + arch_ids->cpus[uid].props.node_id, + local_cpu_id), + 4); + } else { + build_append_int_noprefix(entry, 0, 4); + } + + if (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { + /* IMSIC Base address */ + build_append_int_noprefix(entry, imsic_addr, 8); + /* IMSIC Size */ + build_append_int_noprefix(entry, imsic_size, 4); + } else { + build_append_int_noprefix(entry, 0, 8); + build_append_int_noprefix(entry, 0, 4); + } } static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) @@ -77,6 +102,11 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) MachineClass *mc = MACHINE_GET_CLASS(s); MachineState *ms = MACHINE(s); const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); + uint64_t imsic_socket_addr, imsic_addr; + uint8_t guest_index_bits; + uint32_t imsic_size, local_cpu_id, socket_id; + + guest_index_bits = imsic_num_bits(s->aia_guests + 1); for (int i = 0; i < arch_ids->len; i++) { Aml *dev; @@ -87,8 +117,19 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) aml_append(dev, aml_name_decl("_UID", aml_int(arch_ids->cpus[i].arch_id))); + socket_id = arch_ids->cpus[i].props.node_id; + local_cpu_id = (arch_ids->cpus[i].arch_id - + riscv_socket_first_hartid(ms, socket_id)) % + riscv_socket_hart_count(ms, socket_id); /* build _MAT object */ - riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf); + imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + + (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); + imsic_addr = imsic_socket_addr + + local_cpu_id * IMSIC_HART_SIZE(guest_index_bits); + imsic_size = IMSIC_HART_SIZE(guest_index_bits); + + riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, madt_buf, + s->aia_type, imsic_addr, imsic_size); aml_append(dev, aml_name_decl("_MAT", aml_buffer(madt_buf->len, (uint8_t *)madt_buf->data))); @@ -227,6 +268,7 @@ static void build_dsdt(GArray *table_data, * 5.2.12 Multiple APIC Description Table (MADT) * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15 * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view + * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view */ static void build_madt(GArray *table_data, BIOSLinker *linker, @@ -235,6 +277,12 @@ static void build_madt(GArray *table_data, MachineClass *mc = MACHINE_GET_CLASS(s); MachineState *ms = MACHINE(s); const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); + uint64_t imsic_socket_addr, imsic_addr; + uint8_t guest_index_bits; + uint32_t imsic_size; + uint32_t local_cpu_id, socket_id; + + guest_index_bits = imsic_num_bits(s->aia_guests + 1); AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id, .oem_table_id = s->oem_table_id }; @@ -246,7 +294,17 @@ static void build_madt(GArray *table_data, /* RISC-V Local INTC structures per HART */ for (int i = 0; i < arch_ids->len; i++) { - riscv_acpi_madt_add_rintc(i, arch_ids, table_data); + socket_id = arch_ids->cpus[i].props.node_id; + local_cpu_id = (arch_ids->cpus[i].arch_id - + riscv_socket_first_hartid(ms, socket_id)) % + riscv_socket_hart_count(ms, socket_id); + imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + + (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); + imsic_addr = imsic_socket_addr + + local_cpu_id * IMSIC_HART_SIZE(guest_index_bits); + imsic_size = IMSIC_HART_SIZE(guest_index_bits); + riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, table_data, + s->aia_type, imsic_addr, imsic_size); } acpi_table_end(linker, &table);