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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id nv18-20020a17090b1b5200b0027fee011cebsm1326061pjb.10.2023.10.26.08.20.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 08:20:55 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis Subject: [PATCH v2 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Date: Thu, 26 Oct 2023 23:18:19 +0800 Message-Id: <20231026151828.754279-13-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026151828.754279-1-max.chou@sifive.com> References: <20231026151828.754279-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=max.chou@sifive.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add rv_codec_vror_vi for the vector crypto instruction - vror.vi. The rotate amount of vror.vi is defined by combining seperated bits. Signed-off-by: Max Chou Acked-by: Alistair Francis --- disas/riscv.c | 14 +++++++++++++- disas/riscv.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 8e89e1d1157..ec33e447f5b 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -4011,6 +4011,12 @@ static uint32_t operand_vzimm10(rv_inst inst) return (inst << 34) >> 54; } +static uint32_t operand_vzimm6(rv_inst inst) +{ + return ((inst << 37) >> 63) << 5 | + ((inst << 44) >> 59); +} + static uint32_t operand_bs(rv_inst inst) { return (inst << 32) >> 62; @@ -4393,6 +4399,12 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa) dec->imm = operand_vimm(inst); dec->vm = operand_vm(inst); break; + case rv_codec_vror_vi: + dec->rd = operand_rd(inst); + dec->rs2 = operand_rs2(inst); + dec->imm = operand_vzimm6(inst); + dec->vm = operand_vm(inst); + break; case rv_codec_vsetvli: dec->rd = operand_rd(inst); dec->rs1 = operand_rs1(inst); @@ -4677,7 +4689,7 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) append(buf, tmp, buflen); break; case 'u': - snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111)); + snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b111111)); append(buf, tmp, buflen); break; case 'j': diff --git a/disas/riscv.h b/disas/riscv.h index b242d73b25e..19e5ed2ce63 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -152,6 +152,7 @@ typedef enum { rv_codec_v_i, rv_codec_vsetvli, rv_codec_vsetivli, + rv_codec_vror_vi, rv_codec_zcb_ext, rv_codec_zcb_mul, rv_codec_zcb_lb,