| Message ID | 20231030132058.763556-10-sunilvl@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V: ACPI: Enable AIA, PLIC and update RHCT | expand |
On Mon, Oct 30, 2023 at 11:23 PM Sunil V L <sunilvl@ventanamicro.com> wrote: > > MMU type information is available via MMU node in RHCT. Add this node in > RHCT. > > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/virt-acpi-build.c | 36 +++++++++++++++++++++++++++++++++++- > 1 file changed, 35 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c > index 506d487ede..86c38f7c2b 100644 > --- a/hw/riscv/virt-acpi-build.c > +++ b/hw/riscv/virt-acpi-build.c > @@ -152,6 +152,8 @@ static void build_rhct(GArray *table_data, > size_t len, aligned_len; > uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0; > RISCVCPU *cpu = &s->soc[0].harts[0]; > + uint32_t mmu_offset = 0; > + uint8_t satp_mode_max; > char *isa; > > AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, > @@ -171,6 +173,10 @@ static void build_rhct(GArray *table_data, > num_rhct_nodes++; > } > > + if (cpu->cfg.satp_mode.supported != 0) { > + num_rhct_nodes++; > + } > + > /* Number of RHCT nodes*/ > build_append_int_noprefix(table_data, num_rhct_nodes, 4); > > @@ -226,6 +232,26 @@ static void build_rhct(GArray *table_data, > } > } > > + /* MMU node structure */ > + if (cpu->cfg.satp_mode.supported != 0) { > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + mmu_offset = table_data->len - table.table_offset; > + build_append_int_noprefix(table_data, 2, 2); /* Type */ > + build_append_int_noprefix(table_data, 8, 2); /* Length */ > + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ > + build_append_int_noprefix(table_data, 0, 1); /* Reserved */ > + /* MMU Type */ > + if (satp_mode_max == VM_1_10_SV57) { > + build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ > + } else if (satp_mode_max == VM_1_10_SV48) { > + build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ > + } else if (satp_mode_max == VM_1_10_SV39) { > + build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ > + } else { > + assert(1); > + } > + } > + > /* Hart Info Node */ > for (int i = 0; i < arch_ids->len; i++) { > len = 16; > @@ -238,17 +264,25 @@ static void build_rhct(GArray *table_data, > num_offsets++; > } > > + if (mmu_offset) { > + len += 4; > + num_offsets++; > + } > + > build_append_int_noprefix(table_data, len, 2); > build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ > /* Number of offsets */ > build_append_int_noprefix(table_data, num_offsets, 2); > build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ > - > /* Offsets */ > build_append_int_noprefix(table_data, isa_offset, 4); > if (cmo_offset) { > build_append_int_noprefix(table_data, cmo_offset, 4); > } > + > + if (mmu_offset) { > + build_append_int_noprefix(table_data, mmu_offset, 4); > + } > } > > acpi_table_end(linker, &table); > -- > 2.39.2 > >
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 506d487ede..86c38f7c2b 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -152,6 +152,8 @@ static void build_rhct(GArray *table_data, size_t len, aligned_len; uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0; RISCVCPU *cpu = &s->soc[0].harts[0]; + uint32_t mmu_offset = 0; + uint8_t satp_mode_max; char *isa; AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, @@ -171,6 +173,10 @@ static void build_rhct(GArray *table_data, num_rhct_nodes++; } + if (cpu->cfg.satp_mode.supported != 0) { + num_rhct_nodes++; + } + /* Number of RHCT nodes*/ build_append_int_noprefix(table_data, num_rhct_nodes, 4); @@ -226,6 +232,26 @@ static void build_rhct(GArray *table_data, } } + /* MMU node structure */ + if (cpu->cfg.satp_mode.supported != 0) { + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + mmu_offset = table_data->len - table.table_offset; + build_append_int_noprefix(table_data, 2, 2); /* Type */ + build_append_int_noprefix(table_data, 8, 2); /* Length */ + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ + build_append_int_noprefix(table_data, 0, 1); /* Reserved */ + /* MMU Type */ + if (satp_mode_max == VM_1_10_SV57) { + build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ + } else if (satp_mode_max == VM_1_10_SV48) { + build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ + } else if (satp_mode_max == VM_1_10_SV39) { + build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ + } else { + assert(1); + } + } + /* Hart Info Node */ for (int i = 0; i < arch_ids->len; i++) { len = 16; @@ -238,17 +264,25 @@ static void build_rhct(GArray *table_data, num_offsets++; } + if (mmu_offset) { + len += 4; + num_offsets++; + } + build_append_int_noprefix(table_data, len, 2); build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ /* Number of offsets */ build_append_int_noprefix(table_data, num_offsets, 2); build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ - /* Offsets */ build_append_int_noprefix(table_data, isa_offset, 4); if (cmo_offset) { build_append_int_noprefix(table_data, cmo_offset, 4); } + + if (mmu_offset) { + build_append_int_noprefix(table_data, mmu_offset, 4); + } } acpi_table_end(linker, &table);