From patchwork Thu Nov 2 00:24:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 13443195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4AFBC4167B for ; Thu, 2 Nov 2023 00:35:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyLaM-0005Mv-BH; Wed, 01 Nov 2023 20:29:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyLaE-00053W-Ci for qemu-devel@nongnu.org; Wed, 01 Nov 2023 20:29:14 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyLaB-0000zI-EA for qemu-devel@nongnu.org; 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Thu, 2 Nov 2023 00:29:04 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C569FC1290F; Thu, 2 Nov 2023 00:28:49 +0000 (UTC) From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, philmd@linaro.org, clg@kaod.org, imammedo@redhat.com, imp@bsdimp.com, kevans@freebsd.org, richard.henderson@linaro.org, pbonzini@redhat.com, peter.maydell@linaro.org, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, sundeep.lkml@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com, laurent@vivier.eu, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, mrolnik@gmail.com, edgar.iglesias@gmail.com, bcain@quicinc.com, gaosong@loongson.cn, aurelien@aurel32.net, jiaxun.yang@flygoat.com, aleksandar.rikalo@syrmia.com, chenhuacai@kernel.org, crwulff@gmail.com, marex@denx.de, shorne@gmail.com, npiggin@gmail.com, ysato@users.sourceforge.jp, david@redhat.com, thuth@redhat.com, iii@linux.ibm.com, kbastian@mail.uni-paderborn.de, jcmvbkbc@gmail.com, shan.gavin@gmail.com Subject: [PATCH v4 13/33] target/mips: Use generic helper to show CPU model names Date: Thu, 2 Nov 2023 10:24:40 +1000 Message-ID: <20231102002500.1750692-14-gshan@redhat.com> In-Reply-To: <20231102002500.1750692-1-gshan@redhat.com> References: <20231102002500.1750692-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.8 Received-SPF: pass client-ip=170.10.129.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.393, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For target/mips, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Besides, mips_cpu_list() is reimplemented to dynamically fetch the CPU model names from the registered CPU types , instead of the staticly defined array. Signed-off-by: Gavin Shan --- target/mips/cpu-defs.c.inc | 9 --------- target/mips/cpu.c | 18 ++++++++++++++++++ target/mips/sysemu/mips-qmp-cmds.c | 3 +-- 3 files changed, 19 insertions(+), 11 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index c0c389c59a..fbf787d8ce 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -1018,15 +1018,6 @@ const mips_def_t mips_defs[] = }; const int mips_defs_number = ARRAY_SIZE(mips_defs); -void mips_cpu_list(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { - qemu_printf("MIPS '%s'\n", mips_defs[i].name); - } -} - static void fpu_init (CPUMIPSState *env, const mips_def_t *def) { int i; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a0023edd43..131978563b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -565,6 +565,24 @@ static const struct TCGCPUOps mips_tcg_ops = { }; #endif /* CONFIG_TCG */ +static void mips_cpu_list_entry(gpointer data, gpointer user_data) +{ + const char *typename = object_class_get_name(OBJECT_CLASS(data)); + char *model = cpu_model_from_type(typename); + + qemu_printf(" %s\n", model); + g_free(model); +} + +void mips_cpu_list(void) +{ + GSList *list; + list = object_class_get_list_sorted(TYPE_MIPS_CPU, false); + qemu_printf("Available CPUs:\n"); + g_slist_foreach(list, mips_cpu_list_entry, NULL); + g_slist_free(list); +} + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); diff --git a/target/mips/sysemu/mips-qmp-cmds.c b/target/mips/sysemu/mips-qmp-cmds.c index 6db4626412..7340ac70ba 100644 --- a/target/mips/sysemu/mips-qmp-cmds.c +++ b/target/mips/sysemu/mips-qmp-cmds.c @@ -19,8 +19,7 @@ static void mips_cpu_add_definition(gpointer data, gpointer user_data) typename = object_class_get_name(oc); info = g_malloc0(sizeof(*info)); - info->name = g_strndup(typename, - strlen(typename) - strlen("-" TYPE_MIPS_CPU)); + info->name = cpu_model_from_type(typename); info->q_typename = g_strdup(typename); QAPI_LIST_PREPEND(*cpu_list, info);