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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id k187-20020a633dc4000000b0057c29fec795sm411783pga.37.2023.11.01.17.34.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 17:34:38 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: liweiwei@iscas.ac.cn, Alistair Francis , Alistair Francis , Palmer Dabbelt , alistair23@gmail.com, Bin Meng , Liu Zhiwei , Daniel Henrique Barboza , bmeng.cn@gmail.com Subject: [PATCH 1/2] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled Date: Thu, 2 Nov 2023 10:34:23 +1000 Message-ID: <20231102003424.2003428-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231102003424.2003428-1-alistair.francis@wdc.com> References: <20231102003424.2003428-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=alistair23@gmail.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We currently don't clear the interrupts if they are disabled. This means that if an interrupt occurs and the guest disables interrupts the QEMU IRQ will remain high. This doesn't immediately affect guests, but if the guest re-enables interrupts it's possible that we will miss an interrupt as it always remains set. Let's update the logic to always call qemu_set_irq() even if the interrupts are disabled to ensure we set the level low. The level will never be high unless interrupts are enabled, so we won't generate interrupts when we shouldn't. Signed-off-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- hw/ssi/ibex_spi_host.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index 1ee7d88c22..c300ec294d 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -205,9 +205,10 @@ static void ibex_spi_host_irq(IbexSPIHostState *s) if (err_irq) { s->regs[IBEX_SPI_HOST_INTR_STATE] |= R_INTR_STATE_ERROR_MASK; } - qemu_set_irq(s->host_err, err_irq); } + qemu_set_irq(s->host_err, err_irq); + /* Event IRQ Enabled and Event IRQ Cleared */ if (event_en && !status_pending) { if (FIELD_EX32(intr_test_reg, INTR_STATE, SPI_EVENT)) { @@ -229,8 +230,9 @@ static void ibex_spi_host_irq(IbexSPIHostState *s) if (event_irq) { s->regs[IBEX_SPI_HOST_INTR_STATE] |= R_INTR_STATE_SPI_EVENT_MASK; } - qemu_set_irq(s->event, event_irq); } + + qemu_set_irq(s->event, event_irq); } static void ibex_spi_host_transfer(IbexSPIHostState *s)