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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id ce10-20020a05690c098a00b0059b24bd4f2asm259523ywb.57.2023.11.02.15.45.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 15:45:39 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v9 19/19] target/riscv/tcg: do not support profiles for 'max' CPU Date: Thu, 2 Nov 2023 19:44:45 -0300 Message-ID: <20231102224445.527355-20-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231102224445.527355-1-dbarboza@ventanamicro.com> References: <20231102224445.527355-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1134; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There's no gain in allowing the 'max' CPU to support profiles, since it already contains everything that QEMU can support. And we'll open the door for 'unorthodox' stuff like users disabling profiles of the 'max' CPU. Signed-off-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 553fb337e7..9a964a426e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -825,6 +825,11 @@ static bool riscv_cpu_is_vendor(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) != NULL; } +static bool riscv_cpu_has_max_extensions(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; +} + /* * We'll get here via the following path: * @@ -1003,6 +1008,12 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, return; } + if (riscv_cpu_has_max_extensions(obj)) { + error_setg(errp, "Profile %s is not available for the 'max' CPU", + profile->name); + return; + } + if (cpu->env.misa_mxl != MXL_RV64) { error_setg(errp, "Profile %s only available for 64 bit CPUs", profile->name); @@ -1251,11 +1262,6 @@ static void riscv_init_max_cpu_extensions(Object *obj) } } -static bool riscv_cpu_has_max_extensions(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; -} - static void tcg_cpu_instance_init(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs);