From patchwork Fri Nov 3 03:16:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13444294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D97D1C4332F for ; Fri, 3 Nov 2023 03:19:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qykhQ-0000ex-SJ; Thu, 02 Nov 2023 23:18:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qykhN-0000QE-2d for qemu-devel@nongnu.org; Thu, 02 Nov 2023 23:18:18 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qykh9-0004IT-IB for qemu-devel@nongnu.org; Thu, 02 Nov 2023 23:18:13 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-27d0e3d823fso1451367a91.1 for ; Thu, 02 Nov 2023 20:18:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698981481; x=1699586281; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v93540e6WuPVIuHRRUOeIVZq8uKmhthJTh8ZgKDPGNU=; b=JkC8yc4mJa8pxPZouSRnDTpd09wjA5dui1sJvJLSwFTiLtHu5rGTnZqyqZXIQGk4Ut yltOij/8BdDFTYPuWGu9KeMvWdhmMXr1gJx3Vd1r3eMxAWvwH+iPywEbsPIWFmYeEn3w mWxe9dwj0uMO1fPSDl2meMBV3jX4rPakyU1VrhEe+dOuEhGAc4HrqLzWDWx5cY7uwpuk fggyX79K/9v6TMpU0Y3CYWGgEZcHVF5fFWUbWpsNO5yO7VstUabOhB478YydGI6BukYA VJBZvPi+MliShZ3eVvb1d34eqAJjTN33cZs/mC+P8vPLN36bHq8PSaP1H24pTmgAMRAK +2bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698981481; x=1699586281; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v93540e6WuPVIuHRRUOeIVZq8uKmhthJTh8ZgKDPGNU=; b=VjSmFB4C8sUbbJIvL74JzYfImMIumE7aqMnsCRN7xIIDJUY74d4Xau5aUr1L4ebRUk fu9tUh/k+YeZ0uuQMLAxsAThsGGdI3YJsjAxOLi4cW6Lx95og305TLfSiYxpwOQ5mhdW lQky3zbKoMFxfOKrWBVss8l3buBT/SVqtYlUj9YBJRiTyD6WjIylQ3q32fIX3hiaGxwj +lyDzAGbV+qobLmwXECPwY/QZCOYGkMklOYiGifzYD5TrQieNmb85+Oc2iQcjwuwhXsP c28/0aIzWtlDsPe9gTvVbO9UmpOTDO7u5jDrOpdWpQx25Npptlx+Pl10kFcmD2xXlXuZ kjUw== X-Gm-Message-State: AOJu0YymnmMZZD7c1kuUHjbZN1g+Z7p1LlzOSBam8mqbjoFYTckjlNdx fuRHi1wC0qRz1XlggJ6wjgc6yA== X-Google-Smtp-Source: AGHT+IE3Ilfn62WqlgO/XypxIj2qkqwkP1GTO4JiGtjETaD+0e8ST78Dbq9M0JlcYOsPfHFz2S/qdg== X-Received: by 2002:a17:90b:1d8b:b0:280:19ba:7816 with SMTP id pf11-20020a17090b1d8b00b0028019ba7816mr14590574pjb.10.1698981480944; Thu, 02 Nov 2023 20:18:00 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y17-20020a17090aca9100b0027cf4c554dasm499971pjt.11.2023.11.02.20.17.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 20:18:00 -0700 (PDT) From: Sunil V L To: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Peter Maydell , Shannon Zhao , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Gerd Hoffmann , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anup Patel , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [PATCH v7 10/13] hw/pci-host/gpex: Define properties for MMIO ranges Date: Fri, 3 Nov 2023 08:46:46 +0530 Message-Id: <20231103031649.2769834-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231103031649.2769834-1-sunilvl@ventanamicro.com> References: <20231103031649.2769834-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=sunilvl@ventanamicro.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of making these values machine specific, create properties for the GPEX host bridge with default value 0. During initialization, the firmware can initialize these properties with correct values for the platform. This basically allows DSDT generator code independent of the machine specific memory map accesses. Suggested-by: Igor Mammedov Signed-off-by: Sunil V L Acked-by: Alistair Francis Acked-by: Michael S. Tsirkin Reviewed-by: Daniel Henrique Barboza --- hw/pci-host/gpex-acpi.c | 13 +++++++++++++ hw/pci-host/gpex.c | 12 ++++++++++++ include/hw/pci-host/gpex.h | 28 ++++++++++++++++++++-------- 3 files changed, 45 insertions(+), 8 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 1092dc3b70..f69413ea2c 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -281,3 +281,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) crs_range_set_free(&crs_range_set); } + +void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq) +{ + bool ambig; + Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, &ambig); + + if (!obj || ambig) { + return; + } + + GPEX_HOST(obj)->gpex_cfg.irq = irq; + acpi_dsdt_add_gpex(scope, &GPEX_HOST(obj)->gpex_cfg); +} diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index a6752fac5e..41f4e73f6e 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -154,6 +154,18 @@ static Property gpex_host_properties[] = { */ DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost, allow_unmapped_accesses, true), + DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0), + DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0), + DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0), + DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0), + DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost, + gpex_cfg.mmio32.base, 0), + DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost, + gpex_cfg.mmio32.size, 0), + DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost, + gpex_cfg.mmio64.base, 0), + DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost, + gpex_cfg.mmio64.size, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index b0240bd768..441c6b8b20 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -40,6 +40,15 @@ struct GPEXRootState { /*< public >*/ }; +struct GPEXConfig { + MemMapEntry ecam; + MemMapEntry mmio32; + MemMapEntry mmio64; + MemMapEntry pio; + int irq; + PCIBus *bus; +}; + struct GPEXHost { /*< private >*/ PCIExpressHost parent_obj; @@ -55,19 +64,22 @@ struct GPEXHost { int irq_num[GPEX_NUM_IRQS]; bool allow_unmapped_accesses; -}; -struct GPEXConfig { - MemMapEntry ecam; - MemMapEntry mmio32; - MemMapEntry mmio64; - MemMapEntry pio; - int irq; - PCIBus *bus; + struct GPEXConfig gpex_cfg; }; int gpex_set_irq_num(GPEXHost *s, int index, int gsi); void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg); +void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq); + +#define PCI_HOST_PIO_BASE "pio-base" +#define PCI_HOST_PIO_SIZE "pio-size" +#define PCI_HOST_ECAM_BASE "ecam-base" +#define PCI_HOST_ECAM_SIZE "ecam-size" +#define PCI_HOST_BELOW_4G_MMIO_BASE "below-4g-mmio-base" +#define PCI_HOST_BELOW_4G_MMIO_SIZE "below-4g-mmio-size" +#define PCI_HOST_ABOVE_4G_MMIO_BASE "above-4g-mmio-base" +#define PCI_HOST_ABOVE_4G_MMIO_SIZE "above-4g-mmio-size" #endif /* HW_GPEX_H */