[PULL,00/49] riscv-to-apply queue

Pull-request

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20231107

Message

Alistair Francis Nov. 7, 2023, 2:28 a.m. UTC

The following changes since commit 3e01f1147a16ca566694b97eafc941d62fa1e8d8:

  Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging (2023-11-06 09:34:22 +0800)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20231107

for you to fetch changes up to bc5e8445342fee35b35f2ed9a9f2249e060b8776:

  docs/about/deprecated: Document RISC-V "pmu-num" deprecation (2023-11-07 11:06:02 +1000)

----------------------------------------------------------------
Third RISC-V PR for 8.2

 * Rename ext_icboz to ext_zicboz
 * Rename ext_icbom to ext_zicbom
 * Rename ext_icsr to ext_zicsr
 * Rename ext_ifencei to ext_zifencei
 * Add RISC-V Virtual IRQs and IRQ filtering support
 * Change default linux-user cpu to 'max'
 * Update 'virt' machine core limit
 * Add query-cpu-model-expansion API
 * Rename epmp to smepmp and expose the extension
 * Clear pmp/smepmp bits on reset
 * Ignore pmp writes when RW=01
 * Support zicntr/zihpm flags and disable support
 * Correct CSR_MSECCFG operations
 * Update mail address for Weiwei Li
 * Update RISC-V vector crypto to ratified v1.0.0
 * Clear the Ibex/OpenTitan SPI interrupts even if disabled
 * Set the OpenTitan priv to 1.12.0
 * Support discontinuous PMU counters

----------------------------------------------------------------
Alistair Francis (2):
      hw/ssi: ibex_spi_host: Clear the interrupt even if disabled
      target/riscv: cpu: Set the OpenTitan priv to 1.12.0

Daniel Henrique Barboza (17):
      target/riscv: rename ext_ifencei to ext_zifencei
      target/riscv: rename ext_icsr to ext_zicsr
      target/riscv: rename ext_icbom to ext_zicbom
      target/riscv: rename ext_icboz to ext_zicboz
      linux-user/riscv: change default cpu to 'max'
      docs/system/riscv: update 'virt' machine core limit
      target/riscv/kvm/kvm-cpu.c: add missing property getters()
      qapi,risc-v: add query-cpu-model-expansion
      target/riscv/tcg: add tcg_cpu_finalize_features()
      target/riscv: handle custom props in qmp_query_cpu_model_expansion
      target/riscv: add riscv_cpu_accelerator_compatible()
      target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion
      target/riscv: add zicntr extension flag for TCG
      target/riscv/kvm: add zicntr reg
      target/riscv: add zihpm extension flag for TCG
      target/riscv/kvm: add zihpm reg
      target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot

Heinrich Schuchardt (1):
      target/riscv: correct csr_ops[CSR_MSECCFG]

Himanshu Chauhan (1):
      Add epmp to extensions list and rename it to smepmp

Max Chou (14):
      target/riscv: Add cfg property for Zvkt extension
      target/riscv: Expose Zvkt extension property
      target/riscv: Add cfg property for Zvkb extension
      target/riscv: Replace Zvbb checking by Zvkb
      target/riscv: Expose Zvkb extension property
      target/riscv: Add cfg properties for Zvkn[c|g] extensions
      target/riscv: Expose Zvkn[c|g] extnesion properties
      target/riscv: Add cfg properties for Zvks[c|g] extensions
      target/riscv: Expose Zvks[c|g] extnesion properties
      target/riscv: Move vector crypto extensions to riscv_cpu_extensions
      disas/riscv: Add rv_fmt_vd_vs2_uimm format
      disas/riscv: Add rv_codec_vror_vi for vror.vi
      disas/riscv: Add support for vector crypto extensions
      disas/riscv: Replace TABs with space

Mayuresh Chitale (2):
      target/riscv: pmp: Clear pmp/smepmp bits on reset
      target/riscv: pmp: Ignore writes when RW=01

Rajnesh Kanwal (6):
      target/riscv: Without H-mode mask all HS mode inturrupts in mie.
      target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
      target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
      target/riscv: Split interrupt logic from riscv_cpu_update_mip.
      target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
      target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.

Rob Bradford (5):
      target/riscv: Propagate error from PMU setup
      target/riscv: Don't assume PMU counters are continuous
      target/riscv: Use existing PMU counter mask in FDT generation
      target/riscv: Add "pmu-mask" property to replace "pmu-num"
      docs/about/deprecated: Document RISC-V "pmu-num" deprecation

Weiwei Li (1):
      MAINTAINERS: update mail address for Weiwei Li

 MAINTAINERS                                 |   2 +-
 docs/about/deprecated.rst                   |  12 +
 docs/system/riscv/virt.rst                  |   2 +-
 qapi/machine-target.json                    |   6 +-
 disas/riscv.h                               |   2 +
 linux-user/riscv/target_elf.h               |   3 +-
 target/riscv/cpu.h                          |  25 ++
 target/riscv/cpu_bits.h                     |   6 +
 target/riscv/cpu_cfg.h                      |  22 +-
 target/riscv/pmp.h                          |   2 +
 target/riscv/pmu.h                          |   5 +-
 target/riscv/tcg/tcg-cpu.h                  |   2 +
 disas/riscv.c                               | 157 ++++++++-
 hw/riscv/boot.c                             |   2 +-
 hw/riscv/virt.c                             |   6 +-
 hw/ssi/ibex_spi_host.c                      |   6 +-
 target/riscv/cpu.c                          | 199 ++++++++---
 target/riscv/cpu_helper.c                   |  99 ++++--
 target/riscv/csr.c                          | 497 +++++++++++++++++++++++++---
 target/riscv/gdbstub.c                      |   2 +-
 target/riscv/kvm/kvm-cpu.c                  |  59 +++-
 target/riscv/machine.c                      |  16 +-
 target/riscv/pmp.c                          |  27 +-
 target/riscv/pmu.c                          |  34 +-
 target/riscv/riscv-qmp-cmds.c               | 160 +++++++++
 target/riscv/tcg/tcg-cpu.c                  | 176 +++++++---
 target/riscv/insn_trans/trans_rvi.c.inc     |   2 +-
 target/riscv/insn_trans/trans_rvvk.c.inc    |  37 ++-
 target/riscv/insn_trans/trans_rvzicbo.c.inc |  16 +-
 29 files changed, 1326 insertions(+), 258 deletions(-)

Comments

Stefan Hajnoczi Nov. 7, 2023, 4:59 a.m. UTC | #1

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.