Message ID | 20231113095605.1131443-3-christoph.muellner@vrull.eu (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | RISC-V: Add TSO extensions (Ztso/Ssdtso) | expand |
On 11/13/23 06:56, Christoph Muellner wrote: > From: Christoph Müllner <christoph.muellner@vrull.eu> > > The Ssdtso extension introduces a DTSO field to the {m,s,h}envcfg > register to enable TSO at run-time. Building on top of Ztso support, > this patch treates Ssdtso just like Ztso (always execute in TSO mode), s/treates/treats > which should be fine from a correctness perspective. > > Similar like Ztso, this is expected to have little overhead on > host machines that operate in TSO mode (e.g. x86). > However, executing the TSO fences on guests without TSO, will > have a negative performance impact, regardless if TSO is enabled > in the guest or not (e.g. running a RV guest with Ssdtso and disabled > DTSO bit on an aarch64 host). > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_bits.h | 3 +++ > target/riscv/cpu_cfg.h | 1 + > target/riscv/csr.c | 9 ++++++--- > target/riscv/translate.c | 2 +- > 5 files changed, 13 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b446e553b1..e01bc56471 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -149,6 +149,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > + ISA_EXT_DATA_ENTRY(ssdtso, PRIV_VERSION_1_12_0, ext_ssdtso), > ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), > ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > @@ -1308,6 +1309,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false), > MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false), > MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false), > + MULTI_EXT_CFG_BOOL("ssdtso", ext_ssdtso, false), > MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), > > MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index ebd7917d49..166f1a879d 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -751,6 +751,7 @@ typedef enum RISCVException { > #define MENVCFG_CBIE (3UL << 4) > #define MENVCFG_CBCFE BIT(6) > #define MENVCFG_CBZE BIT(7) > +#define MENVCFG_DTSO BIT(8) > #define MENVCFG_ADUE (1ULL << 61) > #define MENVCFG_PBMTE (1ULL << 62) > #define MENVCFG_STCE (1ULL << 63) > @@ -764,11 +765,13 @@ typedef enum RISCVException { > #define SENVCFG_CBIE MENVCFG_CBIE > #define SENVCFG_CBCFE MENVCFG_CBCFE > #define SENVCFG_CBZE MENVCFG_CBZE > +#define SENVCFG_DTSO MENVCFG_DTSO > > #define HENVCFG_FIOM MENVCFG_FIOM > #define HENVCFG_CBIE MENVCFG_CBIE > #define HENVCFG_CBCFE MENVCFG_CBCFE > #define HENVCFG_CBZE MENVCFG_CBZE > +#define HENVCFG_DTSO MENVCFG_DTSO > #define HENVCFG_ADUE MENVCFG_ADUE > #define HENVCFG_PBMTE MENVCFG_PBMTE > #define HENVCFG_STCE MENVCFG_STCE > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index a0f951d9c1..bdf0d2bbc4 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -72,6 +72,7 @@ struct RISCVCPUConfig { > bool ext_zihpm; > bool ext_ztso; > bool ext_smstateen; > + bool ext_ssdtso; > bool ext_sstc; > bool ext_svadu; > bool ext_svinval; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index fde7ce1a53..ee40f01185 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -2034,7 +2034,8 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > target_ulong val) > { > const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); > - uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; > + uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | > + MENVCFG_CBZE | MENVCFG_DTSO; > > if (riscv_cpu_mxl(env) == MXL_RV64) { > mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | > @@ -2084,7 +2085,8 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno, > static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > target_ulong val) > { > - uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; > + uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | > + SENVCFG_CBZE | SENVCFG_DTSO; > RISCVException ret; > > ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > @@ -2119,7 +2121,8 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > target_ulong val) > { > - uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; > + uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | > + HENVCFG_CBZE | HENVCFG_DTSO; > RISCVException ret; > > ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index ab56051d6d..a9c2061099 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1196,7 +1196,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->cs = cs; > ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); > ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); > - ctx->ztso = cpu->cfg.ext_ztso; > + ctx->ztso = cpu->cfg.ext_ztso || cpu->cfg.ext_ssdtso; > ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); > ctx->zero = tcg_constant_tl(0); > ctx->virt_inst_excp = false;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b446e553b1..e01bc56471 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -149,6 +149,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(ssdtso, PRIV_VERSION_1_12_0, ext_ssdtso), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), @@ -1308,6 +1309,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false), MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false), MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false), + MULTI_EXT_CFG_BOOL("ssdtso", ext_ssdtso, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ebd7917d49..166f1a879d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -751,6 +751,7 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_DTSO BIT(8) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -764,11 +765,13 @@ typedef enum RISCVException { #define SENVCFG_CBIE MENVCFG_CBIE #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE +#define SENVCFG_DTSO MENVCFG_DTSO #define HENVCFG_FIOM MENVCFG_FIOM #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_DTSO MENVCFG_DTSO #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index a0f951d9c1..bdf0d2bbc4 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -72,6 +72,7 @@ struct RISCVCPUConfig { bool ext_zihpm; bool ext_ztso; bool ext_smstateen; + bool ext_ssdtso; bool ext_sstc; bool ext_svadu; bool ext_svinval; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fde7ce1a53..ee40f01185 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2034,7 +2034,8 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); - uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; + uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | + MENVCFG_CBZE | MENVCFG_DTSO; if (riscv_cpu_mxl(env) == MXL_RV64) { mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | @@ -2084,7 +2085,8 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno, static RISCVException write_senvcfg(CPURISCVState *env, int csrno, target_ulong val) { - uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; + uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | + SENVCFG_CBZE | SENVCFG_DTSO; RISCVException ret; ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); @@ -2119,7 +2121,8 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, static RISCVException write_henvcfg(CPURISCVState *env, int csrno, target_ulong val) { - uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; + uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | + HENVCFG_CBZE | HENVCFG_DTSO; RISCVException ret; ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ab56051d6d..a9c2061099 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1196,7 +1196,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cs = cs; ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); - ctx->ztso = cpu->cfg.ext_ztso; + ctx->ztso = cpu->cfg.ext_ztso || cpu->cfg.ext_ssdtso; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero = tcg_constant_tl(0); ctx->virt_inst_excp = false;