diff mbox series

[v5,08/31] target/arm: Use generic cpu_list()

Message ID 20231114235628.534334-9-gshan@redhat.com (mailing list archive)
State New, archived
Headers show
Series Unified CPU type check | expand

Commit Message

Gavin Shan Nov. 14, 2023, 11:56 p.m. UTC
No changes of the output from the following command before and
after it's applied.

[gshan@gshan q]$ ./build/qemu-system-aarch64 -cpu ?
Available CPUs:
  a64fx
  arm1026
  arm1136
  arm1136-r2
  arm1176
  arm11mpcore
  arm926
  arm946
  cortex-a15
  cortex-a35
  cortex-a53
  cortex-a55
  cortex-a57
  cortex-a7
  cortex-a710
  cortex-a72
  cortex-a76
  cortex-a8
  cortex-a9
  cortex-m0
  cortex-m3
  cortex-m33
  cortex-m4
  cortex-m55
  cortex-m7
  cortex-r5
  cortex-r52
  cortex-r5f
  max
  neoverse-n1
  neoverse-n2
  neoverse-v1
  pxa250
  pxa255
  pxa260
  pxa261
  pxa262
  pxa270-a0
  pxa270-a1
  pxa270
  pxa270-b0
  pxa270-b1
  pxa270-c0
  pxa270-c5
  sa1100
  sa1110
  ti925t

Signed-off-by: Gavin Shan <gshan@redhat.com>
---
 target/arm/cpu.h    |  3 ---
 target/arm/helper.c | 46 ---------------------------------------------
 2 files changed, 49 deletions(-)

Comments

Richard Henderson Nov. 15, 2023, 12:41 a.m. UTC | #1
On 11/14/23 15:56, Gavin Shan wrote:
> No changes of the output from the following command before and
> after it's applied.
> 
> [gshan@gshan q]$ ./build/qemu-system-aarch64 -cpu ?
> Available CPUs:
>    a64fx
>    arm1026
>    arm1136
>    arm1136-r2
>    arm1176
>    arm11mpcore
>    arm926
>    arm946
>    cortex-a15
>    cortex-a35
>    cortex-a53
>    cortex-a55
>    cortex-a57
>    cortex-a7
>    cortex-a710
>    cortex-a72
>    cortex-a76
>    cortex-a8
>    cortex-a9
>    cortex-m0
>    cortex-m3
>    cortex-m33
>    cortex-m4
>    cortex-m55
>    cortex-m7
>    cortex-r5
>    cortex-r52
>    cortex-r5f
>    max
>    neoverse-n1
>    neoverse-n2
>    neoverse-v1
>    pxa250
>    pxa255
>    pxa260
>    pxa261
>    pxa262
>    pxa270-a0
>    pxa270-a1
>    pxa270
>    pxa270-b0
>    pxa270-b1
>    pxa270-c0
>    pxa270-c5
>    sa1100
>    sa1110
>    ti925t
> 
> Signed-off-by: Gavin Shan <gshan@redhat.com>
> ---
>   target/arm/cpu.h    |  3 ---
>   target/arm/helper.c | 46 ---------------------------------------------
>   2 files changed, 49 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
Philippe Mathieu-Daudé Nov. 16, 2023, 7:51 a.m. UTC | #2
On 15/11/23 00:56, Gavin Shan wrote:
> No changes of the output from the following command before and
> after it's applied.
> 
> [gshan@gshan q]$ ./build/qemu-system-aarch64 -cpu ?
> Available CPUs:
>    a64fx
>    arm1026
>    arm1136
>    arm1136-r2
>    arm1176
>    arm11mpcore
>    arm926
>    arm946
>    cortex-a15
>    cortex-a35
>    cortex-a53
>    cortex-a55
>    cortex-a57
>    cortex-a7
>    cortex-a710
>    cortex-a72
>    cortex-a76
>    cortex-a8
>    cortex-a9
>    cortex-m0
>    cortex-m3
>    cortex-m33
>    cortex-m4
>    cortex-m55
>    cortex-m7
>    cortex-r5
>    cortex-r52
>    cortex-r5f
>    max
>    neoverse-n1
>    neoverse-n2
>    neoverse-v1
>    pxa250
>    pxa255
>    pxa260
>    pxa261
>    pxa262
>    pxa270-a0
>    pxa270-a1
>    pxa270
>    pxa270-b0
>    pxa270-b1
>    pxa270-c0
>    pxa270-c5
>    sa1100
>    sa1110
>    ti925t
> 
> Signed-off-by: Gavin Shan <gshan@redhat.com>
> ---
>   target/arm/cpu.h    |  3 ---
>   target/arm/helper.c | 46 ---------------------------------------------
>   2 files changed, 49 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a0282e0d28..8c3ca2e231 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2737,7 +2737,6 @@  static inline bool access_secure_reg(CPUARMState *env)
                        (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
                        (_val))
 
-void arm_cpu_list(void);
 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                  uint32_t cur_el, bool secure);
 
@@ -2840,8 +2839,6 @@  bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
 
 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
 
-#define cpu_list arm_cpu_list
-
 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
  *
  * If EL3 is 64-bit:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ff1970981e..c9a8baefc6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9421,52 +9421,6 @@  void register_cp_regs_for_features(ARMCPU *cpu)
 #endif
 }
 
-/* Sort alphabetically by type name, except for "any". */
-static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
-{
-    ObjectClass *class_a = (ObjectClass *)a;
-    ObjectClass *class_b = (ObjectClass *)b;
-    const char *name_a, *name_b;
-
-    name_a = object_class_get_name(class_a);
-    name_b = object_class_get_name(class_b);
-    if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
-        return 1;
-    } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
-        return -1;
-    } else {
-        return strcmp(name_a, name_b);
-    }
-}
-
-static void arm_cpu_list_entry(gpointer data, gpointer user_data)
-{
-    ObjectClass *oc = data;
-    CPUClass *cc = CPU_CLASS(oc);
-    const char *typename;
-    char *name;
-
-    typename = object_class_get_name(oc);
-    name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
-    if (cc->deprecation_note) {
-        qemu_printf("  %s (deprecated)\n", name);
-    } else {
-        qemu_printf("  %s\n", name);
-    }
-    g_free(name);
-}
-
-void arm_cpu_list(void)
-{
-    GSList *list;
-
-    list = object_class_get_list(TYPE_ARM_CPU, false);
-    list = g_slist_sort(list, arm_cpu_list_compare);
-    qemu_printf("Available CPUs:\n");
-    g_slist_foreach(list, arm_cpu_list_entry, NULL);
-    g_slist_free(list);
-}
-
 /*
  * Private utility function for define_one_arm_cp_reg_with_opaque():
  * add a single reginfo struct to the hash table.