Message ID | 20231116120702.53170-1-rcardenas.rod@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Fix SiFive E CLINT clock frequency (#1978) | expand |
I believe you forgot to add your Signed-off-by tag. Without it we can't accept the patch hehe Since you'll need to send another version with the S-o-b, please change the commit title to "riscv: Fix SiFive E CLINT clock frequency" That way other people will quickly identify which sub-tree this patch belongs. The Gitlab bug number you put it in the end of the commit msg in a tag: On 11/16/23 09:07, Román Cárdenas wrote: > If you check the manual of SiFive E310 (https://cdn.sparkfun.com/assets/7/f/0/2/7/fe310-g002-manual-v19p05.pdf?_gl=1*w2ieef*_ga*MTcyNDI2MjM0Ny4xNjk2ODcwNTM3*_ga_T369JS7J9N*MTY5Njg3MDUzNy4xLjAuMTY5Njg3MDUzNy42MC4wLjA.), you can see in Figure 1 that the CLINT is connected to the real time clock, which also feeds the AON peripheral (they share the same clock). > > In page 43, the docs also say that the timer registers of the CLINT count ticks from the rtcclk. > > I am currently playing with bare metal applications both in QEMU and a physical SiFive E310 board and I confirm that the CLINT clock in the physical board runs at 32.768 kHz. In QEMU, the same app produces a completely different outcome, as sometimes a new CLINT interrupt is triggered before finishing other tasks. > > You can check issue #1978 on GitLab for more information. > Like this: Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1978 The rest of the commit msg and the code looks good to me. Thanks, Daniel > --- > hw/riscv/sifive_e.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 0d37adc542..87d9602383 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -225,7 +225,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) > RISCV_ACLINT_SWI_SIZE, > RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, > RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, > - RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); > + SIFIVE_E_LFCLK_DEFAULT_FREQ, false); > sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); > > /* AON */
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 0d37adc542..87d9602383 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -225,7 +225,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, - RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); + SIFIVE_E_LFCLK_DEFAULT_FREQ, false); sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); /* AON */