diff mbox series

target/loongarch: Add timer information dump support

Message ID 20231206081839.2290178-1-maobibo@loongson.cn (mailing list archive)
State New, archived
Headers show
Series target/loongarch: Add timer information dump support | expand

Commit Message

bibo mao Dec. 6, 2023, 8:18 a.m. UTC
Timer emulation sometimes is problematic especially when vm is running in
kvm mode. This patch adds registers dump support relative with timer
hardware, so that it is easier to find the problems.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

gaosong Dec. 6, 2023, 9:47 a.m. UTC | #1
在 2023/12/6 下午4:18, Bibo Mao 写道:
> Timer emulation sometimes is problematic especially when vm is running in
> kvm mode. This patch adds registers dump support relative with timer
> hardware, so that it is easier to find the problems.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/cpu.c | 2 ++
>   1 file changed, 2 insertions(+)

Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index fc075952e6..db9a421cc4 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -762,6 +762,8 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>       qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
>       qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
>       qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
> +    qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
> +    qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
>   
>       /* fpr */
>       if (flags & CPU_DUMP_FPU) {
diff mbox series

Patch

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index fc075952e6..db9a421cc4 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -762,6 +762,8 @@  void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
     qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
     qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
+    qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
+    qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
 
     /* fpr */
     if (flags & CPU_DUMP_FPU) {