diff mbox series

[v2,6/9] Hexagon (target/hexagon) Make generators object oriented - gen_op_regs

Message ID 20231210220712.491494-7-ltaylorsimpson@gmail.com (mailing list archive)
State New, archived
Headers show
Series Hexagon (target/hexagon) Make generators object oriented | expand

Commit Message

Taylor Simpson Dec. 10, 2023, 10:07 p.m. UTC 
Reviewed-by: Brian Cain <bcain@quicinc.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/gen_op_regs.py | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Brian Cain Jan. 11, 2024, 9:09 p.m. UTC | #1 
> -----Original Message-----
> From: Taylor Simpson <ltaylorsimpson@gmail.com>
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain <bcain@quicinc.com>; Matheus Bernardino (QUIC)
> <quic_mathbern@quicinc.com>; Sid Manning <sidneym@quicinc.com>; Marco
> Liebel (QUIC) <quic_mliebel@quicinc.com>; richard.henderson@linaro.org;
> philmd@linaro.org; ale@rev.ng; anjo@rev.ng; ltaylorsimpson@gmail.com
> Subject: [PATCH v2 6/9] Hexagon (target/hexagon) Make generators object
> oriented - gen_op_regs
> 
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
> 
> Reviewed-by: Brian Cain <bcain@quicinc.com>
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>  target/hexagon/gen_op_regs.py | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/target/hexagon/gen_op_regs.py b/target/hexagon/gen_op_regs.py
> index a8a7712129..7b7b33895a 100755
> --- a/target/hexagon/gen_op_regs.py
> +++ b/target/hexagon/gen_op_regs.py
> @@ -70,6 +70,7 @@ def strip_reg_prefix(x):
>  def main():
>      hex_common.read_semantics_file(sys.argv[1])
>      hex_common.read_attribs_file(sys.argv[2])
> +    hex_common.init_registers()
>      tagregs = hex_common.get_tagregs(full=True)
>      tagimms = hex_common.get_tagimms()
> 
> @@ -80,11 +81,12 @@ def main():
>              wregs = []
>              regids = ""
>              for regtype, regid, _, numregs in regs:
> -                if hex_common.is_read(regid):
> +                reg = hex_common.get_register(tag, regtype, regid)
> +                if reg.is_read():
>                      if regid[0] not in regids:
>                          regids += regid[0]
>                      rregs.append(regtype + regid + numregs)
> -                if hex_common.is_written(regid):
> +                if reg.is_written():
>                      wregs.append(regtype + regid + numregs)
>                      if regid[0] not in regids:
>                          regids += regid[0]
> --
> 2.34.1

Reviewed-by: Brian Cain <bcain@quicinc.com>
diff mbox series

Patch

diff --git a/target/hexagon/gen_op_regs.py b/target/hexagon/gen_op_regs.py
index a8a7712129..7b7b33895a 100755
--- a/target/hexagon/gen_op_regs.py
+++ b/target/hexagon/gen_op_regs.py
@@ -70,6 +70,7 @@  def strip_reg_prefix(x):
 def main():
     hex_common.read_semantics_file(sys.argv[1])
     hex_common.read_attribs_file(sys.argv[2])
+    hex_common.init_registers()
     tagregs = hex_common.get_tagregs(full=True)
     tagimms = hex_common.get_tagimms()
 
@@ -80,11 +81,12 @@  def main():
             wregs = []
             regids = ""
             for regtype, regid, _, numregs in regs:
-                if hex_common.is_read(regid):
+                reg = hex_common.get_register(tag, regtype, regid)
+                if reg.is_read():
                     if regid[0] not in regids:
                         regids += regid[0]
                     rregs.append(regtype + regid + numregs)
-                if hex_common.is_written(regid):
+                if reg.is_written():
                     wregs.append(regtype + regid + numregs)
                     if regid[0] not in regids:
                         regids += regid[0]