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[219.106.231.132]) by smtp.gmail.com with ESMTPSA id v23-20020a170902e8d700b001d08e080042sm5842150plg.43.2023.12.10.23.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Dec 2023 23:13:00 -0800 (PST) From: Tomoyuki HIROSE To: qemu-devel@nongnu.org Cc: Tomoyuki HIROSE , Paolo Bonzini , Peter Xu , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 1/2] system/memory.c: support unaligned access Date: Mon, 11 Dec 2023 16:12:03 +0900 Message-Id: <20231211071204.30156-2-tomoyuki.hirose@igel.co.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231211071204.30156-1-tomoyuki.hirose@igel.co.jp> References: <20231211071204.30156-1-tomoyuki.hirose@igel.co.jp> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=tomoyuki.hirose@igel.co.jp; helo=mail-pf1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The previous code ignored 'impl.unaligned' and handled unaligned accesses as is. But this implementation cannot emulate specific registers of some devices that allow unaligned access such as xHCI Host Controller Capability Registers. This commit checks 'impl.unaligned' and if it is false, QEMU emulates unaligned access with multiple aligned access. Signed-off-by: Tomoyuki HIROSE --- system/memory.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/system/memory.c b/system/memory.c index 798b6c0a17..b0caa90fef 100644 --- a/system/memory.c +++ b/system/memory.c @@ -539,6 +539,9 @@ static MemTxResult access_with_adjusted_size(hwaddr addr, unsigned i; MemTxResult r = MEMTX_OK; bool reentrancy_guard_applied = false; + hwaddr aligned_addr; + unsigned corrected_size = size; + signed align_diff = 0; if (!access_size_min) { access_size_min = 1; @@ -560,18 +563,25 @@ static MemTxResult access_with_adjusted_size(hwaddr addr, reentrancy_guard_applied = true; } - /* FIXME: support unaligned access? */ access_size = MAX(MIN(size, access_size_max), access_size_min); access_mask = MAKE_64BIT_MASK(0, access_size * 8); + if (!mr->ops->impl.unaligned) { + aligned_addr = addr & ~(access_size - 1); + align_diff = addr - aligned_addr; + corrected_size = size < access_size ? access_size : + size + (align_diff > 0 ? access_size : 0); + addr = aligned_addr; + } if (memory_region_big_endian(mr)) { - for (i = 0; i < size; i += access_size) { + for (i = 0; i < corrected_size; i += access_size) { r |= access_fn(mr, addr + i, value, access_size, - (size - access_size - i) * 8, access_mask, attrs); + (size - access_size - i + align_diff) * 8, + access_mask, attrs); } } else { - for (i = 0; i < size; i += access_size) { - r |= access_fn(mr, addr + i, value, access_size, i * 8, - access_mask, attrs); + for (i = 0; i < corrected_size; i += access_size) { + r |= access_fn(mr, addr + i, value, access_size, + ((signed)i - align_diff) * 8, access_mask, attrs); } } if (mr->dev && reentrancy_guard_applied) {