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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id bh20-20020a05600c3d1400b0040d15dcb77asm10633674wmb.23.2023.12.21.02.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Dec 2023 02:41:03 -0800 (PST) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Date: Thu, 21 Dec 2023 10:40:35 +0000 Message-Id: <20231221104035.1287244-7-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231221104035.1287244-1-me@deliversmonkey.space> References: <20231221104035.1287244-1-me@deliversmonkey.space> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=baturo.alexey@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 9 +++++++++ target/riscv/cpu_helper.c | 1 + target/riscv/csr.c | 4 ++++ target/riscv/machine.c | 1 + target/riscv/pmp.c | 1 + 5 files changed, 16 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e6571ce99..1d20e6a978 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,6 +153,9 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_12_0, ext_ssnpm), + ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_12_0, ext_smnpm), + ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_12_0, ext_smmpm), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -897,6 +900,7 @@ static void riscv_cpu_reset_hold(Object *obj) pmp_unlock_entries(env); #endif env->xl = riscv_cpu_mxl(env); + riscv_cpu_update_mask(env); cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); @@ -1337,6 +1341,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), + /* Zjpm v0.8 extensions */ + MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), + MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false), + MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false), + MULTI_EXT_CFG_BOOL("zca", ext_zca, false), MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false), MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false), diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8e2751fef4..c2bc737dd7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -723,6 +723,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv = newpriv; env->xl = cpu_recompute_xl(env); + riscv_cpu_update_mask(env); /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a67ba30494..5336d91dd8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1348,6 +1348,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, env->xl = cpu_recompute_xl(env); } + riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } @@ -2039,6 +2040,7 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, } env->menvcfg = (env->menvcfg & ~mask) | (val & mask); + riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } @@ -2093,6 +2095,8 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, } env->senvcfg = (env->senvcfg & ~mask) | (val & mask); + + riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 5e9c5b43ab..41ad30c8e1 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -261,6 +261,7 @@ static int riscv_cpu_post_load(void *opaque, int version_id) CPURISCVState *env = &cpu->env; env->xl = cpu_recompute_xl(env); + riscv_cpu_update_mask(env); return 0; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 893ccd58d8..2cc08e58c5 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -607,6 +607,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val) } env->mseccfg = val; + riscv_cpu_update_mask(env); } /*