| Message ID | 20231224044812.2072140-6-me@deliversmonkey.space (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Pointer Masking update for Zjpm v0.8 | expand |
On 12/24/23 15:48, Alexey Baturo wrote: > From: Alexey Baturo <baturo.alexey@gmail.com> > > Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> > --- > target/riscv/translate.c | 23 +++++++++++++++++++++-- > target/riscv/vector_helper.c | 10 ++++++++++ > 2 files changed, 31 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 1eb501e0d3..c0c5030e05 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -575,11 +575,20 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) > /* Compute a canonical address from a register plus offset. */ > static TCGv get_address(DisasContext *ctx, int rs1, int imm) > { > + int pmlen = riscv_pm_get_pmlen(ctx->pm_pmm); > TCGv addr = tcg_temp_new(); > TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); > > tcg_gen_addi_tl(addr, src1, imm); > - if (get_address_xl(ctx) == MXL_RV32) { > + if (ctx->pm_pmm) { > + tcg_gen_shli_tl(addr, addr, pmlen); > + /* sign extend address by first non-masked bit otherwise zero extend */ > + if (ctx->pm_signext) { > + tcg_gen_sari_tl(addr, addr, pmlen); > + } else { > + tcg_gen_shri_tl(addr, addr, pmlen); > + } > + } else if (get_address_xl(ctx) == MXL_RV32) { > tcg_gen_ext32u_tl(addr, addr); > } > > @@ -589,11 +598,21 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) > /* Compute a canonical address from a register plus reg offset. */ > static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) > { > + int pmlen = riscv_pm_get_pmlen(ctx->pm_pmm); > TCGv addr = tcg_temp_new(); > TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); > > tcg_gen_add_tl(addr, src1, offs); > - if (get_xl(ctx) == MXL_RV32) { > + /* sign extend address by first non-masked bit */ > + if (ctx->pm_pmm) { > + tcg_gen_shli_tl(addr, addr, pmlen); > + /* sign extend address by first non-masked bit otherwise zero extend */ > + if (ctx->pm_signext) { > + tcg_gen_sari_tl(addr, addr, pmlen); > + } else { > + tcg_gen_shri_tl(addr, addr, pmlen); > + } > + } else if (get_xl(ctx) == MXL_RV32) { > tcg_gen_ext32u_tl(addr, addr); Use tcg_gen_{s}extract_tl instead of two shifts. Also, it looks like it would be worth doing all of this once in riscv_tr_init_disas_context: if (get_xl(ctx) == MXL_RV32) { ctx->addr_width = 32; ctx->addr_signed = false; } else { pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM); ctx->addr_width = 64 - riscv_pm_get_pmlen(pm_pmm); ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); } then here in get_address_indexed if (ctx->addr_signed) { tcg_gen_sextract_tl(addr, addr, ctx->addr_width); } else { tcg_gen_extract_tl(addr, addr, ctx->addr_width); } > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 8e7a8e80a0..faa8f5820d 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -94,6 +94,16 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz) > > static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) > { > + RISCVPmPmm pmm = riscv_pm_get_pmm(env); > + int pmlen = riscv_pm_get_pmlen(pmm); > + bool signext = !riscv_cpu_bare_mode(env); > + addr = addr << pmlen; > + /* sign/zero extend masked address by N-1 bit */ > + if (signext) { > + addr = (target_long)addr >> pmlen; > + } else { > + addr = addr >> pmlen; > + } > return addr; > } I think you could usefully exit early when likely(pmm == PMM_FIELD_DISABLED), avoiding the other computation. r~
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1eb501e0d3..c0c5030e05 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -575,11 +575,20 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) /* Compute a canonical address from a register plus offset. */ static TCGv get_address(DisasContext *ctx, int rs1, int imm) { + int pmlen = riscv_pm_get_pmlen(ctx->pm_pmm); TCGv addr = tcg_temp_new(); TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); tcg_gen_addi_tl(addr, src1, imm); - if (get_address_xl(ctx) == MXL_RV32) { + if (ctx->pm_pmm) { + tcg_gen_shli_tl(addr, addr, pmlen); + /* sign extend address by first non-masked bit otherwise zero extend */ + if (ctx->pm_signext) { + tcg_gen_sari_tl(addr, addr, pmlen); + } else { + tcg_gen_shri_tl(addr, addr, pmlen); + } + } else if (get_address_xl(ctx) == MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } @@ -589,11 +598,21 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) /* Compute a canonical address from a register plus reg offset. */ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) { + int pmlen = riscv_pm_get_pmlen(ctx->pm_pmm); TCGv addr = tcg_temp_new(); TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); tcg_gen_add_tl(addr, src1, offs); - if (get_xl(ctx) == MXL_RV32) { + /* sign extend address by first non-masked bit */ + if (ctx->pm_pmm) { + tcg_gen_shli_tl(addr, addr, pmlen); + /* sign extend address by first non-masked bit otherwise zero extend */ + if (ctx->pm_signext) { + tcg_gen_sari_tl(addr, addr, pmlen); + } else { + tcg_gen_shri_tl(addr, addr, pmlen); + } + } else if (get_xl(ctx) == MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } return addr; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8e7a8e80a0..faa8f5820d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -94,6 +94,16 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz) static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) { + RISCVPmPmm pmm = riscv_pm_get_pmm(env); + int pmlen = riscv_pm_get_pmlen(pmm); + bool signext = !riscv_cpu_bare_mode(env); + addr = addr << pmlen; + /* sign/zero extend masked address by N-1 bit */ + if (signext) { + addr = (target_long)addr >> pmlen; + } else { + addr = addr >> pmlen; + } return addr; }