| Message ID | 20231228084051.3235354-4-zhaotianrui@loongson.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add loongarch kvm accel support | expand |
在 2023/12/28 下午4:40, Tianrui Zhao 写道: > Supplement vcpu env initial when vcpu reset, including > init vcpu CSR_CPUID,CSR_TID to cpu->cpu_index. The two > regs will be used in kvm_get/set_csr_ioctl. > > Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> > Signed-off-by: xianglai li <lixianglai@loongson.cn> > --- > target/loongarch/cpu.c | 2 ++ > target/loongarch/cpu.h | 2 +- > 2 files changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Song Gao <gaosong@loongson.cn> Thanks. Song Gao > diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c > index b26187dfde..4432a0081d 100644 > --- a/target/loongarch/cpu.c > +++ b/target/loongarch/cpu.c > @@ -533,10 +533,12 @@ static void loongarch_cpu_reset_hold(Object *obj) > > env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); > env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); > + env->CSR_CPUID = cs->cpu_index; > env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); > env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); > env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); > env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); > + env->CSR_TID = cs->cpu_index; > > env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); > env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); > diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h > index 00d1fba597..f6d5ef0852 100644 > --- a/target/loongarch/cpu.h > +++ b/target/loongarch/cpu.h > @@ -319,6 +319,7 @@ typedef struct CPUArchState { > uint64_t CSR_PWCH; > uint64_t CSR_STLBPS; > uint64_t CSR_RVACFG; > + uint64_t CSR_CPUID; > uint64_t CSR_PRCFG1; > uint64_t CSR_PRCFG2; > uint64_t CSR_PRCFG3; > @@ -350,7 +351,6 @@ typedef struct CPUArchState { > uint64_t CSR_DBG; > uint64_t CSR_DERA; > uint64_t CSR_DSAVE; > - uint64_t CSR_CPUID; > > #ifndef CONFIG_USER_ONLY > LoongArchTLB tlb[LOONGARCH_TLB_MAX];
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b26187dfde..4432a0081d 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -533,10 +533,12 @@ static void loongarch_cpu_reset_hold(Object *obj) env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); + env->CSR_CPUID = cs->cpu_index; env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); + env->CSR_TID = cs->cpu_index; env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 00d1fba597..f6d5ef0852 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -319,6 +319,7 @@ typedef struct CPUArchState { uint64_t CSR_PWCH; uint64_t CSR_STLBPS; uint64_t CSR_RVACFG; + uint64_t CSR_CPUID; uint64_t CSR_PRCFG1; uint64_t CSR_PRCFG2; uint64_t CSR_PRCFG3; @@ -350,7 +351,6 @@ typedef struct CPUArchState { uint64_t CSR_DBG; uint64_t CSR_DERA; uint64_t CSR_DSAVE; - uint64_t CSR_CPUID; #ifndef CONFIG_USER_ONLY LoongArchTLB tlb[LOONGARCH_TLB_MAX];