From patchwork Thu Dec 28 16:06:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?In=C3=A8s_Varhol?= X-Patchwork-Id: 13506122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31413C3DA6E for ; Thu, 28 Dec 2023 16:07:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rIsuY-00024h-9C; Thu, 28 Dec 2023 11:07:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rIsuX-00023m-9d; Thu, 28 Dec 2023 11:07:05 -0500 Received: from zproxy3.enst.fr ([137.194.2.222]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rIsuS-0007D5-Pi; Thu, 28 Dec 2023 11:07:05 -0500 Received: from localhost (localhost [IPv6:::1]) by zproxy3.enst.fr (Postfix) with ESMTP id 7B112A051C; Thu, 28 Dec 2023 17:06:56 +0100 (CET) Received: from zproxy3.enst.fr ([IPv6:::1]) by localhost (zproxy3.enst.fr [IPv6:::1]) (amavis, port 10032) with ESMTP id lTTOrweQ8QvG; Thu, 28 Dec 2023 17:06:55 +0100 (CET) Received: from localhost (localhost [IPv6:::1]) by zproxy3.enst.fr (Postfix) with ESMTP id 969EBA061C; Thu, 28 Dec 2023 17:06:55 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy3.enst.fr 969EBA061C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1703779615; bh=5uCEBuMSY7M2Hzs+ZOpr5gghsD/0jNMVCCBmM93r0u8=; h=From:To:Date:Message-ID:MIME-Version; b=M6wvdE7mPAoGhRXZup2exfTkedg/qDWznyGF9gzujTUVf8CGqsKf58zx2JirerbDs i+w7VKWF8ECymPZrNyhH/fXwd/R2vk/yCvh1WO79Hct2vG3CFpXc/WhMhRGvE496Hd OAZ28EEQeCz+EMHgeVPhdcKKpqT5dHVd7VNK2GR0= X-Virus-Scanned: amavis at enst.fr Received: from zproxy3.enst.fr ([IPv6:::1]) by localhost (zproxy3.enst.fr [IPv6:::1]) (amavis, port 10026) with ESMTP id x3q-iCl8Mg54; Thu, 28 Dec 2023 17:06:55 +0100 (CET) Received: from inesv-Inspiron-3501.lan (unknown [IPv6:2001:861:4680:b1b0:3937:c54c:5417:70d4]) by zproxy3.enst.fr (Postfix) with ESMTPSA id 4AE51A0584; Thu, 28 Dec 2023 17:06:55 +0100 (CET) From: =?utf-8?q?In=C3=A8s_Varhol?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Thomas Huth , =?utf-8?q?In=C3=A8s_Varhol?= , Peter Maydell , Paolo Bonzini , Laurent Vivier , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Arnaud Minier Subject: [PATCH v4 1/3] hw/misc: Implement STM32L4x5 EXTI Date: Thu, 28 Dec 2023 17:06:30 +0100 Message-ID: <20231228160649.299058-2-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231228160649.299058-1-ines.varhol@telecom-paris.fr> References: <20231228160649.299058-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Received-SPF: pass client-ip=137.194.2.222; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy3.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Although very similar to the STM32F4xx EXTI, STM32L4x5 EXTI generates more than 32 event/interrupt requests and thus uses more registers than STM32F4xx EXTI which generates 23 event/interrupt requests. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Acked-by: Alistair Francis --- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/stm32l4x5_exti.c | 288 +++++++++++++++++++++++++++++++ hw/misc/trace-events | 5 + include/hw/misc/stm32l4x5_exti.h | 51 ++++++ 5 files changed, 348 insertions(+) create mode 100644 hw/misc/stm32l4x5_exti.c create mode 100644 include/hw/misc/stm32l4x5_exti.h diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index cc8a8c1418..3efe3dc2cc 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -87,6 +87,9 @@ config STM32F4XX_SYSCFG config STM32F4XX_EXTI bool +config STM32L4X5_EXTI + bool + config MIPS_ITU bool diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 36c20d5637..16db6e228d 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -110,6 +110,7 @@ system_ss.add(when: 'CONFIG_XLNX_VERSAL_TRNG', if_true: files( system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c')) system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c')) system_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c')) +system_ss.add(when: 'CONFIG_STM32L4X5_EXTI', if_true: files('stm32l4x5_exti.c')) system_ss.add(when: 'CONFIG_MPS2_FPGAIO', if_true: files('mps2-fpgaio.c')) system_ss.add(when: 'CONFIG_MPS2_SCC', if_true: files('mps2-scc.c')) diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c new file mode 100644 index 0000000000..81c901d3e5 --- /dev/null +++ b/hw/misc/stm32l4x5_exti.c @@ -0,0 +1,288 @@ +/* + * STM32L4x5 EXTI (Extended interrupts and events controller) + * + * Copyright (c) 2023 Arnaud Minier + * Copyright (c) 2023 Samuel Tardieu + * Copyright (c) 2023 Inès Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * This work is based on the stm32f4xx_exti by Alistair Francis. + * Original code is licensed under the MIT License: + * + * Copyright (c) 2014 Alistair Francis + */ + +/* + * The reference used is the STMicroElectronics RM0351 Reference manual + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/stm32l4x5_exti.h" + +#define EXTI_IMR1 0x00 +#define EXTI_EMR1 0x04 +#define EXTI_RTSR1 0x08 +#define EXTI_FTSR1 0x0C +#define EXTI_SWIER1 0x10 +#define EXTI_PR1 0x14 +#define EXTI_IMR2 0x20 +#define EXTI_EMR2 0x24 +#define EXTI_RTSR2 0x28 +#define EXTI_FTSR2 0x2C +#define EXTI_SWIER2 0x30 +#define EXTI_PR2 0x34 + +#define EXTI_NUM_GPIO_EVENT_IN_LINES 16 + +/* 0b11111111_10000010_00000000_00000000 */ +#define DIRECT_LINE_MASK1 0xFF820000 +/* 0b00000000_00000000_00000000_10000111 */ +#define DIRECT_LINE_MASK2 0x00000087 +/* 0b11111111_11111111_11111111_00000000 */ +#define RESERVED_BITS_MASK2 0xFFFFFF00 + +/* 0b00000000_00000000_00000000_01111000 */ +#define ACTIVABLE_MASK2 (~DIRECT_LINE_MASK2 & ~RESERVED_BITS_MASK2) + +static void stm32l4x5_exti_reset_hold(Object *obj) +{ + Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj); + + s->imr[0] = DIRECT_LINE_MASK1; + s->emr[0] = 0x00000000; + s->rtsr[0] = 0x00000000; + s->ftsr[0] = 0x00000000; + s->swier[0] = 0x00000000; + s->pr[0] = 0x00000000; + + s->imr[1] = DIRECT_LINE_MASK2; + s->emr[1] = 0x00000000; + s->rtsr[1] = 0x00000000; + s->ftsr[1] = 0x00000000; + s->swier[1] = 0x00000000; + s->pr[1] = 0x00000000; +} + +static void stm32l4x5_exti_set_irq(void *opaque, int irq, int level) +{ + Stm32l4x5ExtiState *s = opaque; + const unsigned n = irq >= 32; + const int oirq = irq; + + trace_stm32l4x5_exti_set_irq(irq, level); + + if (irq >= 32) { + /* Shift the value to enable access in x2 registers. */ + irq -= 32; + } + + /* If the interrupt is masked, pr won't be raised */ + if (!((1 << irq) & s->imr[n])) { + return; + } + + if (((1 << irq) & s->rtsr[n]) && level) { + /* Rising Edge */ + s->pr[n] |= 1 << irq; + qemu_irq_pulse(s->irq[oirq]); + } else if (((1 << irq) & s->ftsr[n]) && !level) { + /* Falling Edge */ + s->pr[n] |= 1 << irq; + qemu_irq_pulse(s->irq[oirq]); + } + +} + +static uint64_t stm32l4x5_exti_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Stm32l4x5ExtiState *s = opaque; + uint32_t r = 0; + const unsigned n = addr >= EXTI_IMR2; + + switch (addr) { + case EXTI_IMR1: + case EXTI_IMR2: + r = s->imr[n]; + break; + case EXTI_EMR1: + case EXTI_EMR2: + r = s->emr[n]; + break; + case EXTI_RTSR1: + case EXTI_RTSR2: + r = s->rtsr[n]; + break; + case EXTI_FTSR1: + case EXTI_FTSR2: + r = s->ftsr[n]; + break; + case EXTI_SWIER1: + case EXTI_SWIER2: + r = s->swier[n]; + break; + case EXTI_PR1: + case EXTI_PR2: + r = s->pr[n]; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32L4X5_exti_read: Bad offset 0x%x\n", (int)addr); + break; + } + + trace_stm32l4x5_exti_read(addr, r); + + return r; +} + +static void stm32l4x5_exti_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Stm32l4x5ExtiState *s = opaque; + const uint32_t value = (uint32_t)val64; + + trace_stm32l4x5_exti_write(addr, value); + + switch (addr) { + case EXTI_IMR1: + s->imr[0] = value; + return; + case EXTI_EMR1: + s->emr[0] = value; + return; + case EXTI_RTSR1: + s->rtsr[0] = value & ~DIRECT_LINE_MASK1; + return; + case EXTI_FTSR1: + s->ftsr[0] = value & ~DIRECT_LINE_MASK1; + return; + case EXTI_SWIER1: + const uint32_t set1 = value & ~DIRECT_LINE_MASK1; + const uint32_t pend1 = set1 & ~s->swier[0] & s->imr[0] & ~s->pr[0]; + s->swier[0] = set1; + s->pr[0] |= pend1; + for (int i = 0; i < 32; i++) { + if (pend1 & (1 << i)) { + qemu_irq_pulse(s->irq[i]); + } + } + return; + case EXTI_PR1: + const uint32_t cleared1 = s->pr[0] & value & ~DIRECT_LINE_MASK1; + /* This bit is cleared by writing a 1 to it */ + s->pr[0] &= ~cleared1; + /* Software triggered interrupts are cleared as well */ + s->swier[0] &= ~cleared1; + return; + case EXTI_IMR2: + s->imr[1] = value & ~RESERVED_BITS_MASK2; + return; + case EXTI_EMR2: + s->emr[1] = value & ~RESERVED_BITS_MASK2; + return; + case EXTI_RTSR2: + s->rtsr[1] = value & ACTIVABLE_MASK2; + return; + case EXTI_FTSR2: + s->ftsr[1] = value & ACTIVABLE_MASK2; + return; + case EXTI_SWIER2: + const uint32_t set2 = value & ACTIVABLE_MASK2; + const uint32_t pend2 = set2 & ~s->swier[1] & s->imr[1] & ~s->pr[1]; + s->swier[1] = set2; + s->pr[1] |= pend2; + for (int i = 0; i < 8; i++) { + if (pend2 & (1 << i)) { + qemu_irq_pulse(s->irq[32 + i]); + } + } + return; + case EXTI_PR2: + const uint32_t cleared = s->pr[1] & value & ACTIVABLE_MASK2; + /* This bit is cleared by writing a 1 to it */ + s->pr[1] &= ~cleared; + /* Software triggered interrupts are cleared as well */ + s->swier[1] &= ~cleared; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32L4X5_exti_write: Bad offset 0x%x\n", (int)addr); + } +} + +static const MemoryRegionOps stm32l4x5_exti_ops = { + .read = stm32l4x5_exti_read, + .write = stm32l4x5_exti_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, + .impl.unaligned = false, + .valid.min_access_size = 4, + .valid.max_access_size = 4, + .valid.unaligned = false, +}; + +static void stm32l4x5_exti_init(Object *obj) +{ + Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj); + int i; + + for (i = 0; i < EXTI_NUM_INTERRUPT_OUT_LINES; i++) { + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); + } + + memory_region_init_io(&s->mmio, obj, &stm32l4x5_exti_ops, s, + TYPE_STM32L4X5_EXTI, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq, + EXTI_NUM_GPIO_EVENT_IN_LINES); +} + +static const VMStateDescription vmstate_stm32l4x5_exti = { + .name = TYPE_STM32L4X5_EXTI, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(imr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), + VMSTATE_UINT32_ARRAY(emr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), + VMSTATE_UINT32_ARRAY(rtsr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), + VMSTATE_UINT32_ARRAY(ftsr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), + VMSTATE_UINT32_ARRAY(swier, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), + VMSTATE_UINT32_ARRAY(pr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), + VMSTATE_END_OF_LIST() + } +}; + +static void stm32l4x5_exti_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + dc->vmsd = &vmstate_stm32l4x5_exti; + rc->phases.hold = stm32l4x5_exti_reset_hold; +} + +static const TypeInfo stm32l4x5_exti_types[] = { + { + .name = TYPE_STM32L4X5_EXTI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Stm32l4x5ExtiState), + .instance_init = stm32l4x5_exti_init, + .class_init = stm32l4x5_exti_class_init, + } +}; + +DEFINE_TYPES(stm32l4x5_exti_types) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 05ff692441..2f01c62c0e 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -163,6 +163,11 @@ stm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d" stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" +# stm32l4x5_exti.c +stm32l4x5_exti_set_irq(int irq, int level) "Set EXTI: %d to %d" +stm32l4x5_exti_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" +stm32l4x5_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" + # tz-mpc.c tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" diff --git a/include/hw/misc/stm32l4x5_exti.h b/include/hw/misc/stm32l4x5_exti.h new file mode 100644 index 0000000000..be961d2f01 --- /dev/null +++ b/include/hw/misc/stm32l4x5_exti.h @@ -0,0 +1,51 @@ +/* + * STM32L4x5 EXTI (Extended interrupts and events controller) + * + * Copyright (c) 2023 Arnaud Minier + * Copyright (c) 2023 Inès Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * This work is based on the stm32f4xx_exti by Alistair Francis. + * Original code is licensed under the MIT License: + * + * Copyright (c) 2014 Alistair Francis + */ + +/* + * The reference used is the STMicroElectronics RM0351 Reference manual + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html + */ + +#ifndef HW_STM32L4X5_EXTI_H +#define HW_STM32L4X5_EXTI_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_STM32L4X5_EXTI "stm32l4x5-exti" +OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5ExtiState, STM32L4X5_EXTI) + +#define EXTI_NUM_INTERRUPT_OUT_LINES 40 +#define EXTI_NUM_REGISTER 2 + +struct Stm32l4x5ExtiState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t imr[EXTI_NUM_REGISTER]; + uint32_t emr[EXTI_NUM_REGISTER]; + uint32_t rtsr[EXTI_NUM_REGISTER]; + uint32_t ftsr[EXTI_NUM_REGISTER]; + uint32_t swier[EXTI_NUM_REGISTER]; + uint32_t pr[EXTI_NUM_REGISTER]; + + qemu_irq irq[EXTI_NUM_INTERRUPT_OUT_LINES]; +}; + +#endif