diff mbox series

[v3,01/16] target/riscv/cpu_cfg.h: remove unused fields

Message ID 20240103174013.147279-2-dbarboza@ventanamicro.com (mailing list archive)
State New, archived
Headers show
Series target/riscv: deprecate riscv_cpu_options[] | expand

Commit Message

Daniel Henrique Barboza Jan. 3, 2024, 5:39 p.m. UTC
user_spec, bext_spec and bext_ver aren't being used.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.h     | 1 -
 target/riscv/cpu_cfg.h | 2 --
 2 files changed, 3 deletions(-)

Comments

Alistair Francis Jan. 5, 2024, 3:51 a.m. UTC | #1
On Thu, Jan 4, 2024 at 3:46 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> user_spec, bext_spec and bext_ver aren't being used.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h     | 1 -
>  target/riscv/cpu_cfg.h | 2 --
>  2 files changed, 3 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d74b361be6..40c96a32cc 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -164,7 +164,6 @@ struct CPUArchState {
>      target_ulong guest_phys_fault_addr;
>
>      target_ulong priv_ver;
> -    target_ulong bext_ver;
>      target_ulong vext_ver;
>
>      /* RISCVMXL, but uint32_t for vmstate migration */
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index f4605fb190..c67a8731d3 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -136,8 +136,6 @@ struct RISCVCPUConfig {
>
>      uint32_t pmu_mask;
>      char *priv_spec;
> -    char *user_spec;
> -    char *bext_spec;
>      char *vext_spec;
>      uint16_t vlen;
>      uint16_t elen;
> --
> 2.43.0
>
>
diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d74b361be6..40c96a32cc 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -164,7 +164,6 @@  struct CPUArchState {
     target_ulong guest_phys_fault_addr;
 
     target_ulong priv_ver;
-    target_ulong bext_ver;
     target_ulong vext_ver;
 
     /* RISCVMXL, but uint32_t for vmstate migration */
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index f4605fb190..c67a8731d3 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -136,8 +136,6 @@  struct RISCVCPUConfig {
 
     uint32_t pmu_mask;
     char *priv_spec;
-    char *user_spec;
-    char *bext_spec;
     char *vext_spec;
     uint16_t vlen;
     uint16_t elen;