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[77.11.174.94]) by smtp.gmail.com with ESMTPSA id 3-20020a508e03000000b0055515b40464sm2159752edw.81.2024.01.06.05.25.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jan 2024 05:25:56 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Paolo Bonzini , Marcel Apfelbaum , Bernhard Beschow Subject: [PATCH v2 2/3] hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabled Date: Sat, 6 Jan 2024 14:25:45 +0100 Message-ID: <20240106132546.21248-3-shentey@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240106132546.21248-1-shentey@gmail.com> References: <20240106132546.21248-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=shentey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org QEMU populates the apic_state attribute of x86 CPUs if supported by real hardware or if SMP is active. When handling interrupts, it just checks whether apic_state is populated to route the interrupt to the PIC or to the APIC. However, chapter 10.4.3 of [1] requires that: When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent to an IA-32 processor without an on-chip APIC. This means that when apic_state is populated, QEMU needs to check for the MSR_IA32_APICBASE_ENABLE flag in addition. Implement this which fixes some real-world BIOSes. [1] Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A: System Programming Guide, Part 1 Signed-off-by: Bernhard Beschow --- include/hw/i386/apic.h | 1 + hw/i386/x86.c | 4 ++-- hw/intc/apic_common.c | 13 +++++++++++++ 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index bdc15a7a73..b2907c7179 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -11,6 +11,7 @@ void apic_deliver_nmi(DeviceState *d); int apic_get_interrupt(DeviceState *s); void cpu_set_apic_base(DeviceState *s, uint64_t val); uint64_t cpu_get_apic_base(DeviceState *s); +bool cpu_is_apic_enabled(DeviceState *s); void cpu_set_apic_tpr(DeviceState *s, uint8_t val); uint8_t cpu_get_apic_tpr(DeviceState *s); void apic_init_reset(DeviceState *s); diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 61af705e90..16cd06c594 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -516,7 +516,7 @@ static void x86_nmi(NMIState *n, int cpu_index, Error **errp) CPU_FOREACH(cs) { X86CPU *cpu = X86_CPU(cs); - if (cpu->apic_state) { + if (cpu_is_apic_enabled(cpu->apic_state)) { apic_deliver_nmi(cpu->apic_state); } else { cpu_interrupt(cs, CPU_INTERRUPT_NMI); @@ -551,7 +551,7 @@ static void pic_irq_request(void *opaque, int irq, int level) X86CPU *cpu = X86_CPU(cs); trace_x86_pic_interrupt(irq, level); - if (cpu->apic_state && !kvm_irqchip_in_kernel() && + if (cpu_is_apic_enabled(cpu->apic_state) && !kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { CPU_FOREACH(cs) { cpu = X86_CPU(cs); diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 6c100b48d6..bb5e916e9d 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -63,6 +63,19 @@ uint64_t cpu_get_apic_base(DeviceState *dev) } } +bool cpu_is_apic_enabled(DeviceState *dev) +{ + APICCommonState *s; + + if (!dev) { + return false; + } + + s = APIC_COMMON(dev); + + return s->apicbase & MSR_IA32_APICBASE_ENABLE; +} + void cpu_set_apic_tpr(DeviceState *dev, uint8_t val) { APICCommonState *s;