diff mbox series

[PULL,04/65] target/riscv: Not allow write mstatus_vs without RVV

Message ID 20240110085733.1607526-5-alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions | expand

Commit Message

Alistair Francis Jan. 10, 2024, 8:56 a.m. UTC 
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

If CPU does not implement the Vector extension, it usually means
mstatus vs hardwire to zero. So we should not allow write a
non-zero value to this field.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231215023313.1708-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c50a33397c..d8f751a0ae 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1328,11 +1328,14 @@  static RISCVException write_mstatus(CPURISCVState *env, int csrno,
     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
         MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
-        MSTATUS_TW | MSTATUS_VS;
+        MSTATUS_TW;
 
     if (riscv_has_ext(env, RVF)) {
         mask |= MSTATUS_FS;
     }
+    if (riscv_has_ext(env, RVV)) {
+        mask |= MSTATUS_VS;
+    }
 
     if (xl != MXL_RV32 || env->debugger) {
         if (riscv_has_ext(env, RVH)) {