| Message ID | 20240111161644.33630-2-rbradford@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Add support for 'B' extension | expand |
On Fri, Jan 12, 2024 at 3:38 AM Rob Bradford <rbradford@rivosinc.com> wrote: > > Add the infrastructure for the 'B' extension which is the union of the > Zba, Zbb and Zbs instructions. > > Signed-off-by: Rob Bradford <rbradford@rivosinc.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 5 +++-- > target/riscv/cpu.h | 1 + > target/riscv/tcg/tcg-cpu.c | 1 + > 3 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8cbfc7e781..fc01c10e24 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -38,9 +38,9 @@ > #include "tcg/tcg.h" > > /* RISC-V CPU definitions */ > -static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; > +static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH"; > const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, > - RVC, RVS, RVU, RVH, RVJ, RVG, 0}; > + RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0}; > > /* > * From vector_helper.c > @@ -1299,6 +1299,7 @@ static const MISAExtInfo misa_ext_info_arr[] = { > MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), > MISA_EXT_INFO(RVV, "v", "Vector operations"), > MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), > + MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)") > }; > > static int riscv_validate_misa_info_idx(uint32_t bit) > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5f3955c38d..3843d44fc9 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState; > #define RVH RV('H') > #define RVJ RV('J') > #define RVG RV('G') > +#define RVB RV('B') > > extern const uint32_t misa_bits[]; > const char *riscv_get_misa_ext_name(uint32_t bit); > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 14133ff665..5396c6c3eb 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -1056,6 +1056,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { > MISA_CFG(RVJ, false), > MISA_CFG(RVV, false), > MISA_CFG(RVG, false), > + MISA_CFG(RVB, false), > }; > > /* > -- > 2.43.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbfc7e781..fc01c10e24 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -38,9 +38,9 @@ #include "tcg/tcg.h" /* RISC-V CPU definitions */ -static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; +static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH"; const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, - RVC, RVS, RVU, RVH, RVJ, RVG, 0}; + RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0}; /* * From vector_helper.c @@ -1299,6 +1299,7 @@ static const MISAExtInfo misa_ext_info_arr[] = { MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), MISA_EXT_INFO(RVV, "v", "Vector operations"), MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), + MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)") }; static int riscv_validate_misa_info_idx(uint32_t bit) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5f3955c38d..3843d44fc9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState; #define RVH RV('H') #define RVJ RV('J') #define RVG RV('G') +#define RVB RV('B') extern const uint32_t misa_bits[]; const char *riscv_get_misa_ext_name(uint32_t bit); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 14133ff665..5396c6c3eb 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1056,6 +1056,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { MISA_CFG(RVJ, false), MISA_CFG(RVV, false), MISA_CFG(RVG, false), + MISA_CFG(RVB, false), }; /*