| Message ID | 20240116205817.344178-14-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' | expand |
On Wed, Jan 17, 2024 at 7:03 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > There is no need to keep both 'vlen' and 'vlenb'. All existing code > that requires 'vlen' is retrieving it via 'vlenb << 3'. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 8 +++----- > target/riscv/cpu_cfg.h | 1 - > target/riscv/tcg/tcg-cpu.c | 4 +++- > 3 files changed, 6 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f4261d2ffc..7b3f69d3fb 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1313,7 +1313,6 @@ static void riscv_cpu_init(Object *obj) > > /* Default values for non-bool cpu properties */ > cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16); > - cpu->cfg.vlen = 128; > cpu->cfg.vlenb = 128 >> 3; > cpu->cfg.elen = 64; > cpu->env.vext_ver = VEXT_VERSION_1_00_0; > @@ -1802,22 +1801,21 @@ static void prop_vlen_set(Object *obj, Visitor *v, const char *name, > return; > } > > - if (value != cpu->cfg.vlen && riscv_cpu_is_vendor(obj)) { > + if (value != cpu->cfg.vlenb && riscv_cpu_is_vendor(obj)) { > cpu_set_prop_err(cpu, name, errp); > error_append_hint(errp, "Current '%s' val: %u\n", > - name, cpu->cfg.vlen); > + name, cpu->cfg.vlenb << 3); > return; > } > > cpu_option_add_user_setting(name, value); > - cpu->cfg.vlen = value; > cpu->cfg.vlenb = value >> 3; > } > > static void prop_vlen_get(Object *obj, Visitor *v, const char *name, > void *opaque, Error **errp) > { > - uint16_t value = RISCV_CPU(obj)->cfg.vlen; > + uint16_t value = RISCV_CPU(obj)->cfg.vlenb << 3; > > visit_type_uint16(v, name, &value, errp); > } > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 50479dd72f..e241922f89 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -139,7 +139,6 @@ struct RISCVCPUConfig { > bool ext_XVentanaCondOps; > > uint32_t pmu_mask; > - uint16_t vlen; > uint16_t vlenb; > uint16_t elen; > uint16_t cbom_blocksize; > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index daff0b8f60..667421b0b7 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -298,7 +298,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) > static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > Error **errp) > { > - if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { > + uint32_t vlen = cfg->vlenb << 3; > + > + if (vlen > RV_VLEN_MAX || vlen < 128) { > error_setg(errp, > "Vector extension implementation only supports VLEN " > "in the range [128, %d]", RV_VLEN_MAX); > -- > 2.43.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f4261d2ffc..7b3f69d3fb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1313,7 +1313,6 @@ static void riscv_cpu_init(Object *obj) /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16); - cpu->cfg.vlen = 128; cpu->cfg.vlenb = 128 >> 3; cpu->cfg.elen = 64; cpu->env.vext_ver = VEXT_VERSION_1_00_0; @@ -1802,22 +1801,21 @@ static void prop_vlen_set(Object *obj, Visitor *v, const char *name, return; } - if (value != cpu->cfg.vlen && riscv_cpu_is_vendor(obj)) { + if (value != cpu->cfg.vlenb && riscv_cpu_is_vendor(obj)) { cpu_set_prop_err(cpu, name, errp); error_append_hint(errp, "Current '%s' val: %u\n", - name, cpu->cfg.vlen); + name, cpu->cfg.vlenb << 3); return; } cpu_option_add_user_setting(name, value); - cpu->cfg.vlen = value; cpu->cfg.vlenb = value >> 3; } static void prop_vlen_get(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - uint16_t value = RISCV_CPU(obj)->cfg.vlen; + uint16_t value = RISCV_CPU(obj)->cfg.vlenb << 3; visit_type_uint16(v, name, &value, errp); } diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 50479dd72f..e241922f89 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -139,7 +139,6 @@ struct RISCVCPUConfig { bool ext_XVentanaCondOps; uint32_t pmu_mask; - uint16_t vlen; uint16_t vlenb; uint16_t elen; uint16_t cbom_blocksize; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index daff0b8f60..667421b0b7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -298,7 +298,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { - if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { + uint32_t vlen = cfg->vlenb << 3; + + if (vlen > RV_VLEN_MAX || vlen < 128) { error_setg(errp, "Vector extension implementation only supports VLEN " "in the range [128, %d]", RV_VLEN_MAX);