From patchwork Wed Jan 31 10:13:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13539054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B22AC48285 for ; Wed, 31 Jan 2024 10:01:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rV7PD-0004Ol-57; Wed, 31 Jan 2024 05:01:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rV7P1-0004K1-ID for qemu-devel@nongnu.org; Wed, 31 Jan 2024 05:01:08 -0500 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rV7Oz-0008Lk-Oj for qemu-devel@nongnu.org; Wed, 31 Jan 2024 05:01:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706695265; x=1738231265; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N9Ti/Hwo2aecL2fuF9lq4ptdmphpW+wGySs5h8rhu2o=; b=CumQ9eAtUgHWbjbfPLF9jmlq6LsA3+EjcKNYQwKEhW+tkcKYH4AtElu+ 8Vaz+ArOJ/rXDYgu5rfruFt+4rB0W4R4LYQSXcMAjKrj9KJ4uvMbq3mjQ Yh62oUxTTvHaaQFJ3cXF93Sth2z+dRTSnXMRjBYE2TKBX4COFzOA0nNKI //kxn68d/DeBGGaPnkISR4g03P+IlN1gdUo8DSg/AKm0ICSS7Ckc4gEjD dnf0eMBsm4yAkSfW2aU27iVhcgHrSbcZFWEgg3nCZFxTEAqLtuH9+JPAP CLTbFNNZj7qA2plK1TDSCyMaaw50N18elf1MLMlnNK5XrnZGbvZO7DiYj A==; X-IronPort-AV: E=McAfee;i="6600,9927,10969"; a="25032591" X-IronPort-AV: E=Sophos;i="6.05,231,1701158400"; d="scan'208";a="25032591" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2024 02:01:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,231,1701158400"; d="scan'208";a="4035994" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 31 Jan 2024 02:00:59 -0800 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Babu Moger , Xiaoyao Li , Zhenyu Wang , Zhuocheng Ding , Yongwei Ma , Zhao Liu , Robert Hoo Subject: [PATCH v8 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Date: Wed, 31 Jan 2024 18:13:34 +0800 Message-Id: <20240131101350.109512-6-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131101350.109512-1-zhao1.liu@linux.intel.com> References: <20240131101350.109512-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.292, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Zhao Liu For i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs sharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) to 0, and this means i-cache and d-cache are shared in the SMT level. This is correct if there's single thread per core, but is wrong for the hyper threading case (one core contains multiple threads) since the i-cache and d-cache are shared in the core level other than SMT level. For AMD CPU, commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D") has already introduced i/d cache topology as core level by default. Therefore, in order to be compatible with both multi-threaded and single-threaded situations, we should set i-cache and d-cache be shared at the core level by default. This fix changes the default i/d cache topology from per-thread to per-core. Potentially, this change in L1 cache topology may affect the performance of the VM if the user does not specifically specify the topology or bind the vCPU. However, the way to achieve optimal performance should be to create a reasonable topology and set the appropriate vCPU affinity without relying on QEMU's default topology structure. Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistently") Suggested-by: Robert Hoo Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin --- Changes since v3: * Changed the description of current i/d cache encoding status to avoid misleading to "architectural rules". (Xiaoyao) Changes since v1: * Split this fix from the patch named "i386/cpu: Fix number of addressable IDs in CPUID.04H". * Added the explanation of the impact on performance. (Xiaoyao) --- target/i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 03822d9ba8ee..ba2746c886e3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6112,12 +6112,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, switch (count) { case 0: /* L1 dcache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - 1, cs->nr_cores, + cs->nr_threads, cs->nr_cores, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - 1, cs->nr_cores, + cs->nr_threads, cs->nr_cores, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */