diff mbox series

RISC-V: Report the QEMU vendor/arch IDs on virtual CPUs

Message ID 20240131182430.20174-1-palmer@rivosinc.com (mailing list archive)
State New, archived
Headers show
Series RISC-V: Report the QEMU vendor/arch IDs on virtual CPUs | expand

Commit Message

Palmer Dabbelt Jan. 31, 2024, 6:24 p.m. UTC 
Right now we just report 0 for marchid/mvendorid in QEMU.  That's legal,
but it's tricky for users that want to check if they're running on QEMU
to do so.  This sets marchid to 42, which I've proposed as the QEMU
architecture ID (mvendorid remains 0, just explicitly set, as that's how
the ISA handles open source implementations).

Link: https://github.com/riscv/riscv-isa-manual/pull/1213
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 target/riscv/cpu.c          | 16 ++++++++++++++++
 target/riscv/cpu_vendorid.h |  3 +++
 2 files changed, 19 insertions(+)

Comments

Andrew Jones Feb. 1, 2024, 3:06 p.m. UTC | #1 
On Wed, Jan 31, 2024 at 10:24:30AM -0800, Palmer Dabbelt wrote:
> Right now we just report 0 for marchid/mvendorid in QEMU.  That's legal,
> but it's tricky for users that want to check if they're running on QEMU
> to do so.  This sets marchid to 42, which I've proposed as the QEMU
> architecture ID (mvendorid remains 0, just explicitly set, as that's how
> the ISA handles open source implementations).

Hi Palmer,

marchid has this text

"""
Open-source project architecture IDs are allocated globally by RISC-V
International, and have non-zero architecture IDs with a zero
most-significant-bit (MSB). Commercial architecture IDs are allocated
by each commercial vendor independently, but must have the MSB set and
cannot contain zero in the remaining MXLEN-1 bits.
"""

and mvendorid has this text

"""
...a value of 0 can be
returned to indicate the field is not implemented or that this is a
non-commercial implementation.
"""

We must select zero for mvendorid, since we're a non-commercial
implementation, and that means we can't set the marchid to a commercial
ID of our choosing, i.e. some ID with the MSB set. We also can't select
an archid without the MSB set, though, because RVI needs to allocate
us that ID. Long story short, I think we need to use mvendorid=0,marchid=0
unless we ask for and receive an marchid from RVI. Now, looking at mimpid,
I think we're free to set that to whatever we want, even if the other IDs
must be zero, but we should probably consider if we also want some bits
reserved for revisions or something before settling on an ID. Actually,
my vote would be to get an official marchid from RVI and then mimpid can
be reserved for other uses.

Thanks,
drew



> 
> Link: https://github.com/riscv/riscv-isa-manual/pull/1213
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
>  target/riscv/cpu.c          | 16 ++++++++++++++++
>  target/riscv/cpu_vendorid.h |  3 +++
>  2 files changed, 19 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8cbfc7e781..1aef186f87 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -415,6 +415,9 @@ static void riscv_any_cpu_init(Object *obj)
>      cpu->cfg.ext_zicsr = true;
>      cpu->cfg.mmu = true;
>      cpu->cfg.pmp = true;
> +
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>  
>  static void riscv_max_cpu_init(Object *obj)
> @@ -432,6 +435,8 @@ static void riscv_max_cpu_init(Object *obj)
>      set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
>                                  VM_1_10_SV32 : VM_1_10_SV57);
>  #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>  
>  #if defined(TARGET_RISCV64)
> @@ -445,6 +450,8 @@ static void rv64_base_cpu_init(Object *obj)
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>  #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>  
>  static void rv64_sifive_u_cpu_init(Object *obj)
> @@ -569,6 +576,8 @@ static void rv128_base_cpu_init(Object *obj)
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>  #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>  
>  static void rv64i_bare_cpu_init(Object *obj)
> @@ -591,6 +600,8 @@ static void rv64i_bare_cpu_init(Object *obj)
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64);
>  #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>  #else
>  static void rv32_base_cpu_init(Object *obj)
> @@ -603,6 +614,8 @@ static void rv32_base_cpu_init(Object *obj)
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
>  #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>  
>  static void rv32_sifive_u_cpu_init(Object *obj)
> @@ -672,6 +685,9 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>      cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_zicsr = true;
>      cpu->cfg.pmp = true;
> +
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>  #endif
>  
> diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
> index 96b6b9c2cb..486832cd53 100644
> --- a/target/riscv/cpu_vendorid.h
> +++ b/target/riscv/cpu_vendorid.h
> @@ -7,4 +7,7 @@
>  #define VEYRON_V1_MIMPID        0x111
>  #define VEYRON_V1_MVENDORID     0x61f
>  
> +#define QEMU_VIRT_MVENDORID     0
> +#define QEMU_VIRT_MARCHID       42
> +
>  #endif /*  TARGET_RISCV_CPU_VENDORID_H */
> -- 
> 2.43.0
> 
>
Alistair Francis Feb. 2, 2024, 2:09 a.m. UTC | #2 
On Thu, Feb 1, 2024 at 5:33 AM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> Right now we just report 0 for marchid/mvendorid in QEMU.  That's legal,
> but it's tricky for users that want to check if they're running on QEMU
> to do so.  This sets marchid to 42, which I've proposed as the QEMU
> architecture ID (mvendorid remains 0, just explicitly set, as that's how
> the ISA handles open source implementations).
>
> Link: https://github.com/riscv/riscv-isa-manual/pull/1213

This has been accepted now :)

> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
>  target/riscv/cpu.c          | 16 ++++++++++++++++
>  target/riscv/cpu_vendorid.h |  3 +++
>  2 files changed, 19 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8cbfc7e781..1aef186f87 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -415,6 +415,9 @@ static void riscv_any_cpu_init(Object *obj)
>      cpu->cfg.ext_zicsr = true;
>      cpu->cfg.mmu = true;
>      cpu->cfg.pmp = true;
> +
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>
>  static void riscv_max_cpu_init(Object *obj)
> @@ -432,6 +435,8 @@ static void riscv_max_cpu_init(Object *obj)
>      set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
>                                  VM_1_10_SV32 : VM_1_10_SV57);
>  #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>
>  #if defined(TARGET_RISCV64)
> @@ -445,6 +450,8 @@ static void rv64_base_cpu_init(Object *obj)
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>  #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>
>  static void rv64_sifive_u_cpu_init(Object *obj)
> @@ -569,6 +576,8 @@ static void rv128_base_cpu_init(Object *obj)
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>  #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>
>  static void rv64i_bare_cpu_init(Object *obj)
> @@ -591,6 +600,8 @@ static void rv64i_bare_cpu_init(Object *obj)
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64);
>  #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>  #else
>  static void rv32_base_cpu_init(Object *obj)
> @@ -603,6 +614,8 @@ static void rv32_base_cpu_init(Object *obj)
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
>  #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>
>  static void rv32_sifive_u_cpu_init(Object *obj)
> @@ -672,6 +685,9 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>      cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_zicsr = true;
>      cpu->cfg.pmp = true;
> +
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>  }
>  #endif
>
> diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
> index 96b6b9c2cb..486832cd53 100644
> --- a/target/riscv/cpu_vendorid.h
> +++ b/target/riscv/cpu_vendorid.h
> @@ -7,4 +7,7 @@
>  #define VEYRON_V1_MIMPID        0x111
>  #define VEYRON_V1_MVENDORID     0x61f
>
> +#define QEMU_VIRT_MVENDORID     0
> +#define QEMU_VIRT_MARCHID       42

These aren't used. I think you meant to reference this from the CPU
init functions

Alistair

> +
>  #endif /*  TARGET_RISCV_CPU_VENDORID_H */
> --
> 2.43.0
>
>
Andrew Jones Feb. 2, 2024, 9:20 a.m. UTC | #3 
On Thu, Feb 01, 2024 at 04:06:15PM +0100, Andrew Jones wrote:
> On Wed, Jan 31, 2024 at 10:24:30AM -0800, Palmer Dabbelt wrote:
> > Right now we just report 0 for marchid/mvendorid in QEMU.  That's legal,
> > but it's tricky for users that want to check if they're running on QEMU
> > to do so.  This sets marchid to 42, which I've proposed as the QEMU
> > architecture ID (mvendorid remains 0, just explicitly set, as that's how
> > the ISA handles open source implementations).
> 
> Hi Palmer,
> 
> marchid has this text
> 
> """
> Open-source project architecture IDs are allocated globally by RISC-V
> International, and have non-zero architecture IDs with a zero
> most-significant-bit (MSB). Commercial architecture IDs are allocated
> by each commercial vendor independently, but must have the MSB set and
> cannot contain zero in the remaining MXLEN-1 bits.
> """
> 
> and mvendorid has this text
> 
> """
> ...a value of 0 can be
> returned to indicate the field is not implemented or that this is a
> non-commercial implementation.
> """
> 
> We must select zero for mvendorid, since we're a non-commercial
> implementation, and that means we can't set the marchid to a commercial
> ID of our choosing, i.e. some ID with the MSB set. We also can't select
> an archid without the MSB set, though, because RVI needs to allocate
> us that ID. Long story short, I think we need to use mvendorid=0,marchid=0
> unless we ask for and receive an marchid from RVI. Now, looking at mimpid,
> I think we're free to set that to whatever we want, even if the other IDs
> must be zero, but we should probably consider if we also want some bits
> reserved for revisions or something before settling on an ID. Actually,
> my vote would be to get an official marchid from RVI and then mimpid can
> be reserved for other uses.

So it looks like my vote was the plan all along :-) After reading
Alistair's "this has been approved" comment regarding the Link below I
actually bothered to check it and see that 42 is indeed the official RVI
marchid. That wasn't clear to me from the commit message, but I guess I
should have clicked the link!

Sorry for the noise.

Thanks,
drew

> 
> Thanks,
> drew
> 
> 
> 
> > 
> > Link: https://github.com/riscv/riscv-isa-manual/pull/1213
> > Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> > ---
> >  target/riscv/cpu.c          | 16 ++++++++++++++++
> >  target/riscv/cpu_vendorid.h |  3 +++
> >  2 files changed, 19 insertions(+)
> > 
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 8cbfc7e781..1aef186f87 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -415,6 +415,9 @@ static void riscv_any_cpu_init(Object *obj)
> >      cpu->cfg.ext_zicsr = true;
> >      cpu->cfg.mmu = true;
> >      cpu->cfg.pmp = true;
> > +
> > +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> > +    cpu->cfg.marchid = QEMU_MARCHID;
> >  }
> >  
> >  static void riscv_max_cpu_init(Object *obj)
> > @@ -432,6 +435,8 @@ static void riscv_max_cpu_init(Object *obj)
> >      set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
> >                                  VM_1_10_SV32 : VM_1_10_SV57);
> >  #endif
> > +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> > +    cpu->cfg.marchid = QEMU_MARCHID;
> >  }
> >  
> >  #if defined(TARGET_RISCV64)
> > @@ -445,6 +450,8 @@ static void rv64_base_cpu_init(Object *obj)
> >  #ifndef CONFIG_USER_ONLY
> >      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> >  #endif
> > +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> > +    cpu->cfg.marchid = QEMU_MARCHID;
> >  }
> >  
> >  static void rv64_sifive_u_cpu_init(Object *obj)
> > @@ -569,6 +576,8 @@ static void rv128_base_cpu_init(Object *obj)
> >  #ifndef CONFIG_USER_ONLY
> >      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> >  #endif
> > +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> > +    cpu->cfg.marchid = QEMU_MARCHID;
> >  }
> >  
> >  static void rv64i_bare_cpu_init(Object *obj)
> > @@ -591,6 +600,8 @@ static void rv64i_bare_cpu_init(Object *obj)
> >  #ifndef CONFIG_USER_ONLY
> >      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64);
> >  #endif
> > +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> > +    cpu->cfg.marchid = QEMU_MARCHID;
> >  }
> >  #else
> >  static void rv32_base_cpu_init(Object *obj)
> > @@ -603,6 +614,8 @@ static void rv32_base_cpu_init(Object *obj)
> >  #ifndef CONFIG_USER_ONLY
> >      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> >  #endif
> > +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> > +    cpu->cfg.marchid = QEMU_MARCHID;
> >  }
> >  
> >  static void rv32_sifive_u_cpu_init(Object *obj)
> > @@ -672,6 +685,9 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> >      cpu->cfg.ext_zifencei = true;
> >      cpu->cfg.ext_zicsr = true;
> >      cpu->cfg.pmp = true;
> > +
> > +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> > +    cpu->cfg.marchid = QEMU_MARCHID;
> >  }
> >  #endif
> >  
> > diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
> > index 96b6b9c2cb..486832cd53 100644
> > --- a/target/riscv/cpu_vendorid.h
> > +++ b/target/riscv/cpu_vendorid.h
> > @@ -7,4 +7,7 @@
> >  #define VEYRON_V1_MIMPID        0x111
> >  #define VEYRON_V1_MVENDORID     0x61f
> >  
> > +#define QEMU_VIRT_MVENDORID     0
> > +#define QEMU_VIRT_MARCHID       42
> > +
> >  #endif /*  TARGET_RISCV_CPU_VENDORID_H */
> > -- 
> > 2.43.0
> > 
> >
Daniel Henrique Barboza Feb. 2, 2024, 11:25 a.m. UTC | #4 
On 1/31/24 15:24, Palmer Dabbelt wrote:
> Right now we just report 0 for marchid/mvendorid in QEMU.  That's legal,
> but it's tricky for users that want to check if they're running on QEMU
> to do so.  This sets marchid to 42, which I've proposed as the QEMU
> architecture ID (mvendorid remains 0, just explicitly set, as that's how
> the ISA handles open source implementations).
> 
> Link: https://github.com/riscv/riscv-isa-manual/pull/1213
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---

This patch doesn't compile in my env:

../target/riscv/cpu.c: In function ‘riscv_any_cpu_init’:
../target/riscv/cpu.c:439:26: error: ‘QEMU_MVENDORID’ undeclared (first use in this function); did you mean ‘CSR_MVENDORID’?
   439 |     cpu->cfg.mvendorid = QEMU_MVENDORID;
       |                          ^~~~~~~~~~~~~~
       |                          CSR_MVENDORID
../target/riscv/cpu.c:439:26: note: each undeclared identifier is reported only once for each function it appears in
../target/riscv/cpu.c:440:24: error: ‘QEMU_MARCHID’ undeclared (first use in this function); did you mean ‘QEMU_ARCH’?
   440 |     cpu->cfg.marchid = QEMU_MARCHID;
       |                        ^~~~~~~~~~~~
       |                        QEMU_ARCH


In the patch where I changed 'marchid' (d6a427e2c0b2) I removed the following macro:

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 477f8f8f97..9080d021fa 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -39,11 +39,6 @@
  #include "tcg/tcg.h"
  
  /* RISC-V CPU definitions */
-
-#define RISCV_CPU_MARCHID   ((QEMU_VERSION_MAJOR << 16) | \
-                             (QEMU_VERSION_MINOR << 8)  | \
-                             (QEMU_VERSION_MICRO))
-

So I believe you can re-introduce it as '42' and use it. If you want to be really
explicit you can also re-introduce RISCV_CPU_MVENDORID and RISCV_CPU_MIMPID and
set them all to 0 and use them to assign all machine IDs.

The macro name doesn't matter but I'd not use 'VIRT' in the name. This marchid is
going to be used by any board that uses the CPU, not just the 'virt' board.

One more thing:


>   target/riscv/cpu.c          | 16 ++++++++++++++++
>   target/riscv/cpu_vendorid.h |  3 +++
>   2 files changed, 19 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8cbfc7e781..1aef186f87 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -415,6 +415,9 @@ static void riscv_any_cpu_init(Object *obj)
>       cpu->cfg.ext_zicsr = true;
>       cpu->cfg.mmu = true;
>       cpu->cfg.pmp = true;
> +
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;


Instead of repeating this code in every cpu_init() I would just change post_init():

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 88e8cc8681..f6ef50bb20 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1293,6 +1293,12 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
  
  static void riscv_cpu_post_init(Object *obj)
  {
+    if (!riscv_cpu_is_vendor(obj)) {
+        RISCV_CPU(obj)->cfg.mvendorid = RISCV_CPU_MVENDORID;
+        RISCV_CPU(obj)->cfg.marchid = RISCV_CPU_MARCHID;
+        RISCV_CPU(obj)->cfg.mimpid = RISCV_CPU_MIMPID;
+    }
+
      accel_cpu_instance_init(CPU(obj));
  }

This will change the machine IDs for all CPUs that aren't vendor CPUs, which will
retain whatever value it was set in their cpu_init().


Thanks,


Daniel

>   }
>   
>   static void riscv_max_cpu_init(Object *obj)
> @@ -432,6 +435,8 @@ static void riscv_max_cpu_init(Object *obj)
>       set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
>                                   VM_1_10_SV32 : VM_1_10_SV57);
>   #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>   }
>   
>   #if defined(TARGET_RISCV64)
> @@ -445,6 +450,8 @@ static void rv64_base_cpu_init(Object *obj)
>   #ifndef CONFIG_USER_ONLY
>       set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>   #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>   }
>   
>   static void rv64_sifive_u_cpu_init(Object *obj)
> @@ -569,6 +576,8 @@ static void rv128_base_cpu_init(Object *obj)
>   #ifndef CONFIG_USER_ONLY
>       set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>   #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>   }
>   
>   static void rv64i_bare_cpu_init(Object *obj)
> @@ -591,6 +600,8 @@ static void rv64i_bare_cpu_init(Object *obj)
>   #ifndef CONFIG_USER_ONLY
>       set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64);
>   #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>   }
>   #else
>   static void rv32_base_cpu_init(Object *obj)
> @@ -603,6 +614,8 @@ static void rv32_base_cpu_init(Object *obj)
>   #ifndef CONFIG_USER_ONLY
>       set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
>   #endif
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>   }
>   
>   static void rv32_sifive_u_cpu_init(Object *obj)
> @@ -672,6 +685,9 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>       cpu->cfg.ext_zifencei = true;
>       cpu->cfg.ext_zicsr = true;
>       cpu->cfg.pmp = true;
> +
> +    cpu->cfg.mvendorid = QEMU_MVENDORID;
> +    cpu->cfg.marchid = QEMU_MARCHID;
>   }
>   #endif
>   
> diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
> index 96b6b9c2cb..486832cd53 100644
> --- a/target/riscv/cpu_vendorid.h
> +++ b/target/riscv/cpu_vendorid.h
> @@ -7,4 +7,7 @@
>   #define VEYRON_V1_MIMPID        0x111
>   #define VEYRON_V1_MVENDORID     0x61f
>   
> +#define QEMU_VIRT_MVENDORID     0
> +#define QEMU_VIRT_MARCHID       42
> +
>   #endif /*  TARGET_RISCV_CPU_VENDORID_H */
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8cbfc7e781..1aef186f87 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -415,6 +415,9 @@  static void riscv_any_cpu_init(Object *obj)
     cpu->cfg.ext_zicsr = true;
     cpu->cfg.mmu = true;
     cpu->cfg.pmp = true;
+
+    cpu->cfg.mvendorid = QEMU_MVENDORID;
+    cpu->cfg.marchid = QEMU_MARCHID;
 }
 
 static void riscv_max_cpu_init(Object *obj)
@@ -432,6 +435,8 @@  static void riscv_max_cpu_init(Object *obj)
     set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
                                 VM_1_10_SV32 : VM_1_10_SV57);
 #endif
+    cpu->cfg.mvendorid = QEMU_MVENDORID;
+    cpu->cfg.marchid = QEMU_MARCHID;
 }
 
 #if defined(TARGET_RISCV64)
@@ -445,6 +450,8 @@  static void rv64_base_cpu_init(Object *obj)
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
 #endif
+    cpu->cfg.mvendorid = QEMU_MVENDORID;
+    cpu->cfg.marchid = QEMU_MARCHID;
 }
 
 static void rv64_sifive_u_cpu_init(Object *obj)
@@ -569,6 +576,8 @@  static void rv128_base_cpu_init(Object *obj)
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
 #endif
+    cpu->cfg.mvendorid = QEMU_MVENDORID;
+    cpu->cfg.marchid = QEMU_MARCHID;
 }
 
 static void rv64i_bare_cpu_init(Object *obj)
@@ -591,6 +600,8 @@  static void rv64i_bare_cpu_init(Object *obj)
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64);
 #endif
+    cpu->cfg.mvendorid = QEMU_MVENDORID;
+    cpu->cfg.marchid = QEMU_MARCHID;
 }
 #else
 static void rv32_base_cpu_init(Object *obj)
@@ -603,6 +614,8 @@  static void rv32_base_cpu_init(Object *obj)
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
 #endif
+    cpu->cfg.mvendorid = QEMU_MVENDORID;
+    cpu->cfg.marchid = QEMU_MARCHID;
 }
 
 static void rv32_sifive_u_cpu_init(Object *obj)
@@ -672,6 +685,9 @@  static void rv32_imafcu_nommu_cpu_init(Object *obj)
     cpu->cfg.ext_zifencei = true;
     cpu->cfg.ext_zicsr = true;
     cpu->cfg.pmp = true;
+
+    cpu->cfg.mvendorid = QEMU_MVENDORID;
+    cpu->cfg.marchid = QEMU_MARCHID;
 }
 #endif
 
diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
index 96b6b9c2cb..486832cd53 100644
--- a/target/riscv/cpu_vendorid.h
+++ b/target/riscv/cpu_vendorid.h
@@ -7,4 +7,7 @@ 
 #define VEYRON_V1_MIMPID        0x111
 #define VEYRON_V1_MVENDORID     0x61f
 
+#define QEMU_VIRT_MVENDORID     0
+#define QEMU_VIRT_MARCHID       42
+
 #endif /*  TARGET_RISCV_CPU_VENDORID_H */