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[219.106.231.132]) by smtp.gmail.com with ESMTPSA id 38-20020a631366000000b005d6c208fbd2sm11943780pgt.35.2024.02.01.00.14.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 00:14:30 -0800 (PST) From: Tomoyuki HIROSE To: qemu-devel@nongnu.org Cc: Tomoyuki HIROSE , Paolo Bonzini , Peter Xu , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/2] system/memory.c: support unaligned access Date: Thu, 1 Feb 2024 17:13:12 +0900 Message-Id: <20240201081313.1339788-2-tomoyuki.hirose@igel.co.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240201081313.1339788-1-tomoyuki.hirose@igel.co.jp> References: <20240201081313.1339788-1-tomoyuki.hirose@igel.co.jp> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=tomoyuki.hirose@igel.co.jp; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The previous code ignored 'impl.unaligned' and handled unaligned accesses as is. But this implementation cannot emulate specific registers of some devices that allow unaligned access such as xHCI Host Controller Capability Registers. This commit checks 'impl.unaligned' and if it is false, QEMU emulates unaligned access with multiple aligned access. Signed-off-by: Tomoyuki HIROSE --- system/memory.c | 38 +++++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/system/memory.c b/system/memory.c index a229a79988..a7ca0c9f54 100644 --- a/system/memory.c +++ b/system/memory.c @@ -535,10 +535,17 @@ static MemTxResult access_with_adjusted_size(hwaddr addr, MemTxAttrs attrs) { uint64_t access_mask; + unsigned access_mask_shift; + unsigned access_mask_start_offset; + unsigned access_mask_end_offset; unsigned access_size; - unsigned i; MemTxResult r = MEMTX_OK; bool reentrancy_guard_applied = false; + bool is_big_endian = memory_region_big_endian(mr); + signed start_diff; + signed current_offset; + signed access_shift; + hwaddr current_addr; if (!access_size_min) { access_size_min = 1; @@ -560,19 +567,24 @@ static MemTxResult access_with_adjusted_size(hwaddr addr, reentrancy_guard_applied = true; } - /* FIXME: support unaligned access? */ access_size = MAX(MIN(size, access_size_max), access_size_min); - access_mask = MAKE_64BIT_MASK(0, access_size * 8); - if (memory_region_big_endian(mr)) { - for (i = 0; i < size; i += access_size) { - r |= access_fn(mr, addr + i, value, access_size, - (size - access_size - i) * 8, access_mask, attrs); - } - } else { - for (i = 0; i < size; i += access_size) { - r |= access_fn(mr, addr + i, value, access_size, i * 8, - access_mask, attrs); - } + start_diff = mr->ops->impl.unaligned ? 0 : addr & (access_size - 1); + current_addr = addr - start_diff; + for (current_offset = -start_diff; current_offset < (signed)size; + current_offset += access_size, current_addr += access_size) { + access_shift = is_big_endian + ? (signed)size - (signed)access_size - current_offset + : current_offset; + access_mask_shift = current_offset > 0 ? 0 : -current_offset; + access_mask_start_offset = current_offset > 0 ? current_offset : 0; + access_mask_end_offset = current_offset + access_size > size + ? size + : current_offset + access_size; + access_mask = MAKE_64BIT_MASK(access_mask_shift * 8, + (access_mask_end_offset - access_mask_start_offset) * 8); + + r |= access_fn(mr, current_addr, value, access_size, access_shift * 8, + access_mask, attrs); } if (mr->dev && reentrancy_guard_applied) { mr->dev->mem_reentrancy_guard.engaged_in_io = false;