Message ID | 20240212171320.47361-2-irina.ryapolova@syntacore.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [1/2] target/riscv/csr.c: Add functional of hvictl CSR | expand |
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0c21145eaf..51b1099e10 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1136,7 +1136,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, static const uint64_t delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; static const uint64_t vs_delegable_ints = - (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP; + VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \