[v5,36/41] Add mailbox property tests. Part 1

Message ID	20240219011739.2316619-37-sergey.kambalin@auriga.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Sergey Kambalin <serg.oker@gmail.com> To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Sergey Kambalin <sergey.kambalin@auriga.com> Subject: [PATCH v5 36/41] Add mailbox property tests. Part 1 Date: Sun, 18 Feb 2024 19:17:34 -0600 Message-Id: <20240219011739.2316619-37-sergey.kambalin@auriga.com> In-Reply-To: <20240219011739.2316619-1-sergey.kambalin@auriga.com> References: <20240219011739.2316619-1-sergey.kambalin@auriga.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1134; envelope-from=serg.oker@gmail.com; helo=mail-yw1-x1134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	Raspberry Pi 4B machine \| expand [v5,00/41] Raspberry Pi 4B machine [v5,01/41] Split out common part of BCM283X classes [v5,02/41] Split out common part of peripherals [v5,03/41] Split out raspi machine common part [v5,04/41] Introduce BCM2838 SoC [v5,05/41] Add GIC-400 to BCM2838 SoC [v5,06/41] Add BCM2838 GPIO stub [v5,07/41] Implement BCM2838 GPIO functionality [v5,08/41] Connect SD controller to BCM2838 GPIO [v5,09/41] Add GPIO and SD to BCM2838 periph [v5,10/41] Introduce Raspberry PI 4 machine [v5,11/41] Temporarily disable unimplemented rpi4b devices [v5,12/41] Add memory region for BCM2837 RPiVid ASB [v5,13/41] Add BCM2838 PCIE Root Complex [v5,14/41] Add BCM2838 PCIE host [v5,15/41] Enable BCM2838 PCIE [v5,16/41] Add RPi4 RNG200 [v5,17/41] Implement BCM2838 thermal sensor [v5,18/41] Add clock_isp stub [v5,19/41] Add GENET stub [v5,20/41] Add GENET register structs. Part 1 [v5,21/41] Add GENET register structs. Part 2 [v5,22/41] Add GENET register structs. Part 3 [v5,23/41] Add GENET register structs. Part 4 [v5,24/41] Add GENET register access macros [v5,25/41] Implement GENET register ops [v5,26/41] Implement GENET MDIO [v5,27/41] Implement GENET TX path [v5,28/41] Implement GENET RX path [v5,29/41] Enable BCM2838 GENET controller [v5,30/41] Add Rpi4b boot tests [v5,31/41] Add mailbox test stub [v5,32/41] Add mailbox test constants [v5,33/41] Add mailbox tests tags. Part 1 [v5,34/41] Add mailbox tests tags. Part 2 [v5,35/41] Add mailbox tests tags. Part 3 [v5,36/41] Add mailbox property tests. Part 1 [v5,37/41] Add mailbox property tests. Part 2 [v5,38/41] Add mailbox property tests. Part 3 [v5,39/41] Add missed BCM2835 properties [v5,40/41] Append added properties to mailbox test [v5,41/41] Add RPi4B to paspi.rst

diff --git a/tests/qtest/bcm2838-mailbox.c b/tests/qtest/bcm2838-mailbox.c index 1efd3c628a..0928a3dff8 100644 --- a/tests/qtest/bcm2838-mailbox.c +++ b/tests/qtest/bcm2838-mailbox.c @@ -11,7 +11,6 @@ #include "hw/registerfields.h" #include "libqtest-single.h" #include "bcm2838-mailbox.h" -#include "hw/arm/raspberrypi-fw-defs.h" REG32(MBOX_EXCHNG_REG, 0) FIELD(MBOX_EXCHNG_REG, CHANNEL, 0, 4) diff --git a/tests/qtest/bcm2838-mbox-property-test.c b/tests/qtest/bcm2838-mbox-property-test.c new file mode 100644 index 0000000000..acb421915b --- /dev/null +++ b/tests/qtest/bcm2838-mbox-property-test.c @@ -0,0 +1,207 @@ +/* + * Tests set for BCM2838 mailbox property interface. + * + * Copyright (c) 2022 Auriga + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/registerfields.h" +#include "libqtest-single.h" +#include "bcm2838-mailbox.h" +#include "hw/arm/raspberrypi-fw-defs.h" + +REG32(MBOX_SIZE_STAT, 0) +FIELD(MBOX_SIZE_STAT, SIZE, 0, 31) +FIELD(MBOX_SIZE_STAT, SUCCESS, 31, 1) + +REG32(SET_POWER_STATE_CMD, 0) +FIELD(SET_POWER_STATE_CMD, EN, 0, 1) +FIELD(SET_POWER_STATE_CMD, WAIT, 1, 1) + +REG32(GET_CLOCK_STATE_CMD, 0) +FIELD(GET_CLOCK_STATE_CMD, EN, 0, 1) +FIELD(GET_CLOCK_STATE_CMD, NPRES, 1, 1) + +#define MBOX_TEST_MESSAGE_ADDRESS 0x10000000 + +#define TEST_TAG(x) RPI_FWREQ_ ## x +#define TEST_TAG_TYPE(x) TAG_##x##_t + +#define TEST_FN_NAME(test, subtest) \ + test ## _ ## subtest ## _test + +#define SETUP_FN_NAME(test, subtest) \ + test ## _ ## subtest ## _setup + +#define CHECK_FN_NAME(test, subtest) \ + test ## _ ## subtest ## _spec_check + +#define DECLARE_TEST_CASE_SETUP(testname, ...) \ + void SETUP_FN_NAME(testname, __VA_ARGS__) \ + (TEST_TAG_TYPE(testname) * tag) + +/*----------------------------------------------------------------------------*/ +#define DECLARE_TEST_CASE(testname, ...) \ + __attribute__((weak)) \ + void SETUP_FN_NAME(testname, __VA_ARGS__) \ + (TEST_TAG_TYPE(testname) * tag); \ + static void CHECK_FN_NAME(testname, __VA_ARGS__) \ + (TEST_TAG_TYPE(testname) *tag); \ + static void TEST_FN_NAME(testname, __VA_ARGS__)(void) { \ + struct { \ + MboxBufHeader header; \ + TEST_TAG_TYPE(testname) tag; \ + uint32_t end_tag; \ + } mailbox_buffer = { 0 }; \ + \ + QTestState *qts = qtest_init("-machine raspi4b-2g"); \ + \ + mailbox_buffer.header.size = sizeof(mailbox_buffer); \ + mailbox_buffer.header.req_resp_code = MBOX_PROCESS_REQUEST; \ + \ + mailbox_buffer.tag.id = TEST_TAG(testname); \ + mailbox_buffer.tag.value_buffer_size = MAX( \ + sizeof(mailbox_buffer.tag.request.value), \ + sizeof(mailbox_buffer.tag.response.value)); \ + mailbox_buffer.tag.request.zero = 0; \ + \ + mailbox_buffer.end_tag = RPI_FWREQ_PROPERTY_END; \ + \ + if (SETUP_FN_NAME(testname, __VA_ARGS__)) { \ + SETUP_FN_NAME(testname, __VA_ARGS__)(&mailbox_buffer.tag); \ + } \ + \ + qtest_memwrite(qts, MBOX_TEST_MESSAGE_ADDRESS, \ + &mailbox_buffer, sizeof(mailbox_buffer)); \ + qtest_mbox1_write_message(qts, MBOX_CHANNEL_ID_PROPERTY, \ + MBOX_TEST_MESSAGE_ADDRESS); \ + \ + qtest_mbox0_read_message(qts, MBOX_CHANNEL_ID_PROPERTY, \ + &mailbox_buffer, sizeof(mailbox_buffer)); \ + \ + g_assert_cmphex(mailbox_buffer.header.req_resp_code, ==, MBOX_SUCCESS);\ + \ + g_assert_cmphex(mailbox_buffer.tag.id, ==, TEST_TAG(testname)); \ + \ + uint32_t size = FIELD_EX32(mailbox_buffer.tag.response.size_stat, \ + MBOX_SIZE_STAT, SIZE); \ + uint32_t success = FIELD_EX32(mailbox_buffer.tag.response.size_stat, \ + MBOX_SIZE_STAT, SUCCESS); \ + g_assert_cmpint(size, ==, sizeof(mailbox_buffer.tag.response.value)); \ + g_assert_cmpint(success, ==, 1); \ + \ + CHECK_FN_NAME(testname, __VA_ARGS__)(&mailbox_buffer.tag); \ + \ + qtest_quit(qts); \ + } \ + static void CHECK_FN_NAME(testname, __VA_ARGS__) \ + (TEST_TAG_TYPE(testname) * tag) + +/*----------------------------------------------------------------------------*/ + +#define QTEST_ADD_TEST_CASE(testname, ...) \ + qtest_add_func(stringify(/bcm2838/mbox/property/ \ + TEST_FN_NAME(testname, __VA_ARGS__)-test), \ + TEST_FN_NAME(testname, __VA_ARGS__)) + +/*----------------------------------------------------------------------------*/ +DECLARE_TEST_CASE(GET_FIRMWARE_REVISION) { + g_assert_cmpint(tag->response.value.revision, ==, FIRMWARE_REVISION); +} + +// /*----------------------------------------------------------------------------*/ +DECLARE_TEST_CASE(GET_BOARD_REVISION) { + g_assert_cmpint(tag->response.value.revision, ==, BOARD_REVISION); +} + +/*----------------------------------------------------------------------------*/ +DECLARE_TEST_CASE(GET_ARM_MEMORY) { + g_assert_cmphex(tag->response.value.base, ==, ARM_MEMORY_BASE); + g_assert_cmphex(tag->response.value.size, ==, ARM_MEMORY_SIZE); +} + +/*----------------------------------------------------------------------------*/ +DECLARE_TEST_CASE(GET_VC_MEMORY) { + g_assert_cmphex(tag->response.value.base, ==, VC_MEMORY_BASE); + g_assert_cmphex(tag->response.value.size, ==, VC_MEMORY_SIZE); +} + +/*----------------------------------------------------------------------------*/ +DECLARE_TEST_CASE(SET_POWER_STATE) { + uint32_t enabled = + FIELD_EX32(tag->response.value.cmd, SET_POWER_STATE_CMD, EN); + uint32_t wait = + FIELD_EX32(tag->response.value.cmd, SET_POWER_STATE_CMD, WAIT); + g_assert_cmphex(tag->response.value.device_id, ==, DEVICE_ID_UART0); + g_assert_cmpint(enabled, ==, 1); + g_assert_cmpint(wait, ==, 0); +} +DECLARE_TEST_CASE_SETUP(SET_POWER_STATE) { + tag->request.value.device_id = DEVICE_ID_UART0; + tag->response.value.cmd = + FIELD_DP32(tag->response.value.cmd, SET_POWER_STATE_CMD, EN, 1); + tag->response.value.cmd = + FIELD_DP32(tag->response.value.cmd, SET_POWER_STATE_CMD, WAIT, 1); +} + +/*----------------------------------------------------------------------------*/ +DECLARE_TEST_CASE(GET_CLOCK_STATE) { + uint32_t enabled = + FIELD_EX32(tag->response.value.cmd, GET_CLOCK_STATE_CMD, EN); + uint32_t not_present = + FIELD_EX32(tag->response.value.cmd, GET_CLOCK_STATE_CMD, NPRES); + g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_CORE); + g_assert_cmphex(enabled, ==, 1); + g_assert_cmphex(not_present, ==, 0); +} +DECLARE_TEST_CASE_SETUP(GET_CLOCK_STATE) { + tag->request.value.clock_id = CLOCK_ID_CORE; +} + +/*----------------------------------------------------------------------------*/ +DECLARE_TEST_CASE(GET_CLOCK_RATE, EMMC) { + g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_EMMC); + g_assert_cmphex(tag->response.value.rate, ==, CLOCK_RATE_EMMC); +} +DECLARE_TEST_CASE_SETUP(GET_CLOCK_RATE, EMMC) { + tag->request.value.clock_id = CLOCK_ID_EMMC; +} + +/*----------------------------------------------------------------------------*/ +DECLARE_TEST_CASE(GET_MAX_CLOCK_RATE, EMMC) { + g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_EMMC); + g_assert_cmphex(tag->response.value.rate, ==, CLOCK_RATE_EMMC); +} +DECLARE_TEST_CASE_SETUP(GET_MAX_CLOCK_RATE, EMMC) { + tag->request.value.clock_id = CLOCK_ID_EMMC; +} + +/*----------------------------------------------------------------------------*/ +DECLARE_TEST_CASE(GET_MIN_CLOCK_RATE, EMMC) { + g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_EMMC); + g_assert_cmphex(tag->response.value.rate, ==, CLOCK_RATE_EMMC); +} +DECLARE_TEST_CASE_SETUP(GET_MIN_CLOCK_RATE, EMMC) { + tag->request.value.clock_id = CLOCK_ID_EMMC; +} + +/*----------------------------------------------------------------------------*/ +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + QTEST_ADD_TEST_CASE(GET_FIRMWARE_REVISION); + QTEST_ADD_TEST_CASE(GET_BOARD_REVISION); + QTEST_ADD_TEST_CASE(GET_ARM_MEMORY); + QTEST_ADD_TEST_CASE(GET_VC_MEMORY); + QTEST_ADD_TEST_CASE(SET_POWER_STATE); + QTEST_ADD_TEST_CASE(GET_CLOCK_STATE); + QTEST_ADD_TEST_CASE(GET_CLOCK_RATE, EMMC); + QTEST_ADD_TEST_CASE(GET_MAX_CLOCK_RATE, EMMC); + QTEST_ADD_TEST_CASE(GET_MIN_CLOCK_RATE, EMMC); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index e312634963..6d829d35dd 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -229,7 +229,7 @@ qtests_aarch64 = \ ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \ (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ (config_all_devices.has_key('CONFIG_XLNX_VERSAL') ? ['xlnx-canfd-test', 'xlnx-versal-trng-test'] : []) + \ - (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ + (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test', 'bcm2838-mbox-property-test'] : []) + \ (config_all_accel.has_key('CONFIG_TCG') and \ config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \ ['arm-cpu-features',

[v5,36/41] Add mailbox property tests. Part 1

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Patch