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[176.184.23.7]) by smtp.gmail.com with ESMTPSA id m8-20020a05600c4f4800b00411fb769583sm15737715wmq.27.2024.02.20.11.26.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Feb 2024 11:26:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Alex_Benn=C3=A9e?= , Mark Cave-Ayland , Bernhard Beschow , Richard Henderson , Markus Armbruster , Alexander Graf , Anton Johansson , Paolo Bonzini , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 2/2] hw/alpha/typhoon: Set CPU IRQs using QDev API Date: Tue, 20 Feb 2024 20:26:25 +0100 Message-ID: <20240220192625.17944-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240220192625.17944-1-philmd@linaro.org> References: <20240220192625.17944-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philmd@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Keep a reference of CPU IRQs in the TyphoonCchip state. Resolve them once in typhoon_init(), and access them with the qemu_irq API. Signed-off-by: Philippe Mathieu-Daudé --- hw/alpha/typhoon.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index e8711ae16a..f038b6f000 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -26,6 +26,8 @@ typedef struct TyphoonCchip { uint64_t dim[4]; uint32_t iic[4]; AlphaCPU *cpu[4]; + qemu_irq cpu_tmr[4]; + qemu_irq cpu_smp[4]; } TyphoonCchip; typedef struct TyphoonWindow { @@ -343,17 +345,16 @@ static MemTxResult cchip_write(void *opaque, hwaddr addr, for (i = 0; i < 4; ++i) { AlphaCPU *cpu = s->cchip.cpu[i]; if (cpu != NULL) { - CPUState *cs = CPU(cpu); /* IPI can be either cleared or set by the write. */ if (newval & (1 << (i + 8))) { - cpu_interrupt(cs, CPU_INTERRUPT_SMP); + qemu_irq_raise(s->cchip.cpu_smp[i]); } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP); + qemu_irq_lower(s->cchip.cpu_smp[i]); } /* ITI can only be cleared by the write. */ if ((newval & (1 << (i + 4))) == 0) { - cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER); + qemu_irq_lower(s->cchip.cpu_tmr[i]); } } } @@ -802,7 +803,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level) /* Set the ITI bit for this cpu. */ s->cchip.misc |= 1 << (i + 4); /* And signal the interrupt. */ - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER); + qemu_irq_raise(s->cchip.cpu_tmr[i]); } } } @@ -815,7 +816,7 @@ static void typhoon_alarm_timer(void *opaque) /* Set the ITI bit for this cpu. */ s->cchip.misc |= 1 << (cpu + 4); - cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER); + qemu_irq_raise(s->cchip.cpu_tmr[cpu]); } PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq, @@ -845,6 +846,8 @@ PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq, cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, typhoon_alarm_timer, (void *)((uintptr_t)s + i)); + s->cchip.cpu_tmr[i] = qdev_get_gpio_in_named(DEVICE(cpu), "TMR", 0); + s->cchip.cpu_smp[i] = qdev_get_gpio_in_named(DEVICE(cpu), "SMP", 0); } }