Message ID | 20240221130823.677762-11-ruanjinjie@huawei.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI | expand |
On 2/21/24 03:08, Jinjie Ruan via wrote: > Set or clear PSTATE.ALLINT on taking an exception to ELx according to the > SCTLR_ELx.SPINTMASK bit. > > Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> > --- > target/arm/helper.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 62c8e5d611..952ea7c02a 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -11540,6 +11540,15 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) > } > } > > + if (cpu_isar_feature(aa64_nmi, cpu) && > + (env->cp15.sctlr_el[new_el] & SCTLR_NMI)) { > + if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPINTMASK)) { > + new_mode |= PSTATE_ALLINT; > + } else { > + new_mode &= ~PSTATE_ALLINT; > + } > + } new_mode starts at zero and adds state as required -- there is no need to clear allint here... though I see that we do the same for SSBS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/helper.c b/target/arm/helper.c index 62c8e5d611..952ea7c02a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11540,6 +11540,15 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) } } + if (cpu_isar_feature(aa64_nmi, cpu) && + (env->cp15.sctlr_el[new_el] & SCTLR_NMI)) { + if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPINTMASK)) { + new_mode |= PSTATE_ALLINT; + } else { + new_mode &= ~PSTATE_ALLINT; + } + } + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = true; aarch64_restore_sp(env, new_el);
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the SCTLR_ELx.SPINTMASK bit. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+)