From patchwork Wed Feb 21 13:08:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinjie Ruan X-Patchwork-Id: 13565730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C560C48BEB for ; Wed, 21 Feb 2024 15:34:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcoOP-0001ld-IT; Wed, 21 Feb 2024 10:20:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcoJp-0000wk-23; Wed, 21 Feb 2024 10:15:33 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcmLz-0004pz-4H; Wed, 21 Feb 2024 08:09:40 -0500 Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4TfxPz0n4zz2BdDH; Wed, 21 Feb 2024 21:07:19 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id 121BB1400CF; Wed, 21 Feb 2024 21:09:28 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 21 Feb 2024 21:09:27 +0800 To: , , , , , , CC: Subject: [RFC PATCH v2 07/22] target/arm: Add support for NMI event state Date: Wed, 21 Feb 2024 13:08:08 +0000 Message-ID: <20240221130823.677762-8-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240221130823.677762-1-ruanjinjie@huawei.com> References: <20240221130823.677762-1-ruanjinjie@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass client-ip=45.249.212.190; envelope-from=ruanjinjie@huawei.com; helo=szxga04-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan X-Patchwork-Original-From: Jinjie Ruan via From: Jinjie Ruan Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The NMI exception state include whether the interrupt with super priority is IRQ or FIQ, so add a nmi_is_irq flag in CPUARMState to distinguish it. Signed-off-by: Jinjie Ruan --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5257343bcb..051e589e19 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -603,6 +603,8 @@ typedef struct CPUArchState { /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ uint32_t irq_line_state; + bool nmi_is_irq; + /* Thumb-2 EE state. */ uint32_t teecr; uint32_t teehbr; diff --git a/target/arm/helper.c b/target/arm/helper.c index bd7858e02e..0bd7a87e51 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10575,6 +10575,15 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); hcr = hcr_el2 & HCR_FMO; break; + case EXCP_NMI: + if (env->nmi_is_irq) { + scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); + hcr = hcr_el2 & HCR_IMO; + } else { + scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); + hcr = hcr_el2 & HCR_FMO; + } + break; default: scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); hcr = hcr_el2 & HCR_AMO;