| Message ID | 20240223103221.1142518-15-ruanjinjie@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI | expand |
On 2/23/24 00:32, Jinjie Ruan via wrote: > Add GICR_INMIR0 register and support access GICR_INMIR0. > > Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> > --- > hw/intc/arm_gicv3_redist.c | 23 +++++++++++++++++++++++ > hw/intc/gicv3_internal.h | 1 + > 2 files changed, 24 insertions(+) > > diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c > index 8153525849..87e7823f34 100644 > --- a/hw/intc/arm_gicv3_redist.c > +++ b/hw/intc/arm_gicv3_redist.c > @@ -35,6 +35,15 @@ static int gicr_ns_access(GICv3CPUState *cs, int irq) > return extract32(cs->gicr_nsacr, irq * 2, 2); > } > > +static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, > + uint32_t *reg, uint32_t val) > +{ > + /* Helper routine to implement writing to a "set" register */ > + val &= mask_group(cs, attrs); > + *reg = val; > + gicv3_redist_update(cs); > +} > + > static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, > uint32_t *reg, uint32_t val) > { > @@ -406,6 +415,13 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, > *data = value; > return MEMTX_OK; > } > + case GICR_INMIR0: > + if (!cs->gic->nmi_support) { > + *data = 0; > + return MEMTX_OK; > + } > + *data = gicr_read_bitmap_reg(cs, attrs, cs->gicr_isuperprio); > + return MEMTX_OK; Clearer as *data = (cs->gic->nmi_support ? gicr_read_bitmap_reg(cs, attrs, cs->gicr_isuperprio) : 0); return MEMTX_OK; > + case GICR_INMIR0: > + if (!cs->gic->nmi_support) { > + return MEMTX_OK; > + } > + gicr_write_bitmap_reg(cs, attrs, &cs->gicr_isuperprio, value); > + return MEMTX_OK; Likewise, if (cs->gic->nmi_support) { gicr_write_bitmap_reg(cs, attrs, &cs->gicr_isuperprio, value); } return MEMTX_OK; r~
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 8153525849..87e7823f34 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -35,6 +35,15 @@ static int gicr_ns_access(GICv3CPUState *cs, int irq) return extract32(cs->gicr_nsacr, irq * 2, 2); } +static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, + uint32_t *reg, uint32_t val) +{ + /* Helper routine to implement writing to a "set" register */ + val &= mask_group(cs, attrs); + *reg = val; + gicv3_redist_update(cs); +} + static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, uint32_t *reg, uint32_t val) { @@ -406,6 +415,13 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, *data = value; return MEMTX_OK; } + case GICR_INMIR0: + if (!cs->gic->nmi_support) { + *data = 0; + return MEMTX_OK; + } + *data = gicr_read_bitmap_reg(cs, attrs, cs->gicr_isuperprio); + return MEMTX_OK; case GICR_ICFGR0: case GICR_ICFGR1: { @@ -555,6 +571,13 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, gicv3_redist_update(cs); return MEMTX_OK; } + case GICR_INMIR0: + if (!cs->gic->nmi_support) { + return MEMTX_OK; + } + gicr_write_bitmap_reg(cs, attrs, &cs->gicr_isuperprio, value); + return MEMTX_OK; + case GICR_ICFGR0: /* Register is all RAZ/WI or RAO/WI bits */ return MEMTX_OK; diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 29d5cdc1b6..f35b7d2f03 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -109,6 +109,7 @@ #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04) #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) +#define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80) /* VLPI redistributor registers, offsets from VLPI_base */ #define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70)
Add GICR_INMIR0 register and support access GICR_INMIR0. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> --- hw/intc/arm_gicv3_redist.c | 23 +++++++++++++++++++++++ hw/intc/gicv3_internal.h | 1 + 2 files changed, 24 insertions(+)