Message ID | 20240223103221.1142518-8-ruanjinjie@huawei.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI | expand |
On 2/23/24 00:32, Jinjie Ruan via wrote: > According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt > with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in > arm_phys_excp_target_el(). > > Signed-off-by: Jinjie Ruan<ruanjinjie@huawei.com> > --- > v3: > - Remove nmi_is_irq flag in CPUARMState. > - Handle NMI same as IRQ in arm_phys_excp_target_el() > --- > target/arm/helper.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/helper.c b/target/arm/helper.c index 376e0d91ff..2f54413b01 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10571,6 +10571,7 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, hcr_el2 = arm_hcr_el2_eff(env); switch (excp_idx) { case EXCP_IRQ: + case EXCP_NMI: scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); hcr = hcr_el2 & HCR_IMO; break;
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in arm_phys_excp_target_el(). Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> --- v3: - Remove nmi_is_irq flag in CPUARMState. - Handle NMI same as IRQ in arm_phys_excp_target_el() --- target/arm/helper.c | 1 + 1 file changed, 1 insertion(+)