| Message ID | 20240227103231.1556302-8-zhao1.liu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce smp.modules for x86 in QEMU | expand |
On 2/27/24 04:32, Zhao Liu wrote: > From: Zhao Liu <zhao1.liu@intel.com> > > The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information > for cpuid 0x8000001D") adds the cache topology for AMD CPU by encoding > the number of sharing threads directly. > > From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14]) > means [1]: > > The number of logical processors sharing this cache is the value of > this field incremented by 1. To determine which logical processors are > sharing a cache, determine a Share Id for each processor as follows: > > ShareId = LocalApicId >> log2(NumSharingCache+1) > > Logical processors with the same ShareId then share a cache. If > NumSharingCache+1 is not a power of two, round it up to the next power > of two. > > From the description above, the calculation of this field should be same > as CPUID[4].EAX[bits 25:14] for Intel CPUs. So also use the offsets of > APIC ID to calculate this field. > > [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology > Information > > Cc: Babu Moger <babu.moger@amd.com> > Tested-by: Yongwei Ma <yongwei.ma@intel.com> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Babu Moger <babu.moger@amd.com> > --- > Changes since v7: > * Moved this patch after CPUID[4]'s similar change ("i386/cpu: Use APIC > ID offset to encode cache topo in CPUID[4]"). (Xiaoyao) > * Dropped Michael/Babu's Acked/Reviewed/Tested tags since the code > change due to the rebase. > * Re-added Yongwei's Tested tag For his re-testing (compilation on > Intel platforms). > > Changes since v3: > * Rewrote the subject. (Babu) > * Deleted the original "comment/help" expression, as this behavior is > confirmed for AMD CPUs. (Babu) > * Renamed "num_apic_ids" (v3) to "num_sharing_cache" to match spec > definition. (Babu) > > Changes since v1: > * Renamed "l3_threads" to "num_apic_ids" in > encode_cache_cpuid8000001d(). (Yanan) > * Added the description of the original commit and add Cc. > --- > target/i386/cpu.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index c77bcbc44d59..df56c7a449c8 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -331,7 +331,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, > uint32_t *eax, uint32_t *ebx, > uint32_t *ecx, uint32_t *edx) > { > - uint32_t l3_threads; > + uint32_t num_sharing_cache; > assert(cache->size == cache->line_size * cache->associativity * > cache->partitions * cache->sets); > > @@ -340,11 +340,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, > > /* L3 is shared among multiple cores */ > if (cache->level == 3) { > - l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; > - *eax |= (l3_threads - 1) << 14; > + num_sharing_cache = 1 << apicid_die_offset(topo_info); > } else { > - *eax |= ((topo_info->threads_per_core - 1) << 14); > + num_sharing_cache = 1 << apicid_core_offset(topo_info); > } > + *eax |= (num_sharing_cache - 1) << 14; > > assert(cache->line_size > 0); > assert(cache->partitions > 0);
On 2/27/2024 6:32 PM, Zhao Liu wrote: > From: Zhao Liu <zhao1.liu@intel.com> > > The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information > for cpuid 0x8000001D") adds the cache topology for AMD CPU by encoding > the number of sharing threads directly. > > From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14]) > means [1]: > > The number of logical processors sharing this cache is the value of > this field incremented by 1. To determine which logical processors are > sharing a cache, determine a Share Id for each processor as follows: > > ShareId = LocalApicId >> log2(NumSharingCache+1) > > Logical processors with the same ShareId then share a cache. If > NumSharingCache+1 is not a power of two, round it up to the next power > of two. > > From the description above, the calculation of this field should be same > as CPUID[4].EAX[bits 25:14] for Intel CPUs. So also use the offsets of > APIC ID to calculate this field. > > [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology > Information > > Cc: Babu Moger <babu.moger@amd.com> > Tested-by: Yongwei Ma <yongwei.ma@intel.com> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> > --- > Changes since v7: > * Moved this patch after CPUID[4]'s similar change ("i386/cpu: Use APIC > ID offset to encode cache topo in CPUID[4]"). (Xiaoyao) > * Dropped Michael/Babu's Acked/Reviewed/Tested tags since the code > change due to the rebase. > * Re-added Yongwei's Tested tag For his re-testing (compilation on > Intel platforms). > > Changes since v3: > * Rewrote the subject. (Babu) > * Deleted the original "comment/help" expression, as this behavior is > confirmed for AMD CPUs. (Babu) > * Renamed "num_apic_ids" (v3) to "num_sharing_cache" to match spec > definition. (Babu) > > Changes since v1: > * Renamed "l3_threads" to "num_apic_ids" in > encode_cache_cpuid8000001d(). (Yanan) > * Added the description of the original commit and add Cc. > --- > target/i386/cpu.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index c77bcbc44d59..df56c7a449c8 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -331,7 +331,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, > uint32_t *eax, uint32_t *ebx, > uint32_t *ecx, uint32_t *edx) > { > - uint32_t l3_threads; > + uint32_t num_sharing_cache; > assert(cache->size == cache->line_size * cache->associativity * > cache->partitions * cache->sets); > > @@ -340,11 +340,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, > > /* L3 is shared among multiple cores */ > if (cache->level == 3) { > - l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; > - *eax |= (l3_threads - 1) << 14; > + num_sharing_cache = 1 << apicid_die_offset(topo_info); > } else { > - *eax |= ((topo_info->threads_per_core - 1) << 14); > + num_sharing_cache = 1 << apicid_core_offset(topo_info); > } > + *eax |= (num_sharing_cache - 1) << 14; > > assert(cache->line_size > 0); > assert(cache->partitions > 0);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c77bcbc44d59..df56c7a449c8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -331,7 +331,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t l3_threads; + uint32_t num_sharing_cache; assert(cache->size == cache->line_size * cache->associativity * cache->partitions * cache->sets); @@ -340,11 +340,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, /* L3 is shared among multiple cores */ if (cache->level == 3) { - l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; - *eax |= (l3_threads - 1) << 14; + num_sharing_cache = 1 << apicid_die_offset(topo_info); } else { - *eax |= ((topo_info->threads_per_core - 1) << 14); + num_sharing_cache = 1 << apicid_core_offset(topo_info); } + *eax |= (num_sharing_cache - 1) << 14; assert(cache->line_size > 0); assert(cache->partitions > 0);