| Message ID | 20240228081028.35081-1-hrak1529@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Fix privilege mode of G-stage translation for debugging | expand |
On Wed, Feb 28, 2024 at 10:14 PM Hiroaki Yamamoto <hrak1529@gmail.com> wrote: > > G-stage translation should be considered to be user-level access in riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill(). > > This fixes a bug that prevents gdb from reading memory while the VM is running in VS-mode. Thanks for the patch. In the future can you ensure your commit message wraps at around 70 characters? > > Signed-off-by: Hiroaki Yamamoto <hrak1529@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index d462d95ee1..6e13069da7 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1212,7 +1212,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) > > if (env->virt_enabled) { > if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, > - 0, mmu_idx, false, true, true)) { > + 0, MMUIdx_U, false, true, true)) { > return -1; > } > } > -- > 2.43.2 > >
On Wed, Feb 28, 2024 at 10:14 PM Hiroaki Yamamoto <hrak1529@gmail.com> wrote: > > G-stage translation should be considered to be user-level access in riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill(). > > This fixes a bug that prevents gdb from reading memory while the VM is running in VS-mode. > > Signed-off-by: Hiroaki Yamamoto <hrak1529@gmail.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index d462d95ee1..6e13069da7 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1212,7 +1212,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) > > if (env->virt_enabled) { > if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, > - 0, mmu_idx, false, true, true)) { > + 0, MMUIdx_U, false, true, true)) { > return -1; > } > } > -- > 2.43.2 > >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d462d95ee1..6e13069da7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1212,7 +1212,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) if (env->virt_enabled) { if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, - 0, mmu_idx, false, true, true)) { + 0, MMUIdx_U, false, true, true)) { return -1; } }
G-stage translation should be considered to be user-level access in riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill(). This fixes a bug that prevents gdb from reading memory while the VM is running in VS-mode. Signed-off-by: Hiroaki Yamamoto <hrak1529@gmail.com> --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)