| Message ID | 20240228092946.1768728-3-ruanjinjie@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI | expand |
On 2/27/24 23:29, Jinjie Ruan via wrote: > When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to > ELx, with or without superpriority is masked. > > As Richard suggested, place ALLINT bit in PSTATE in env->pstate. > > With the change to pstate_read/write, exception entry > and return are automatically handled. > > Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> > --- > v4: > - Keep PSTATE.ALLINT in env->pstate but not env->allint. > - Update the commit message. > v3: > - Remove ALLINT dump in aarch64_cpu_dump_state(). > - Update the commit message. > --- > target/arm/cpu.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 63f31e0d98..d6c3f8a935 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -224,6 +224,7 @@ typedef struct CPUArchState { > * semantics as for AArch32, as described in the comments on each field) > * nRW (also known as M[4]) is kept, inverted, in env->aarch64 > * DAIF (exception masks) are kept in env->daif > + * ALLINT (all IRQ or FIQ interrupts masks) are kept in env->pstate No need for this comment addition, because it is covered by... > * BTYPE is kept in env->btype > * SM and ZA are kept in env->svcr > * all other bits are stored in their correct places in env->pstate ... this existing line. With that, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 63f31e0d98..d6c3f8a935 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -224,6 +224,7 @@ typedef struct CPUArchState { * semantics as for AArch32, as described in the comments on each field) * nRW (also known as M[4]) is kept, inverted, in env->aarch64 * DAIF (exception masks) are kept in env->daif + * ALLINT (all IRQ or FIQ interrupts masks) are kept in env->pstate * BTYPE is kept in env->btype * SM and ZA are kept in env->svcr * all other bits are stored in their correct places in env->pstate @@ -1543,6 +1544,7 @@ FIELD(VTCR, SL2, 33, 1) #define PSTATE_D (1U << 9) #define PSTATE_BTYPE (3U << 10) #define PSTATE_SSBS (1U << 12) +#define PSTATE_ALLINT (1U << 13) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22)
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to ELx, with or without superpriority is masked. As Richard suggested, place ALLINT bit in PSTATE in env->pstate. With the change to pstate_read/write, exception entry and return are automatically handled. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> --- v4: - Keep PSTATE.ALLINT in env->pstate but not env->allint. - Update the commit message. v3: - Remove ALLINT dump in aarch64_cpu_dump_state(). - Update the commit message. --- target/arm/cpu.h | 2 ++ 1 file changed, 2 insertions(+)