| Message ID | 20240229131039.1868904-20-ruanjinjie@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI | expand |
On 2/29/24 03:10, Jinjie Ruan via wrote: > In CPU Interface, if the IRQ has the superpriority property, report > NMI to the corresponding PE. > > Signed-off-by: Jinjie Ruan<ruanjinjie@huawei.com> > --- > v4: > - Swap the ordering of the IFs. > v3: > - Remove handling nmi_is_irq flag. > --- > hw/intc/arm_gicv3_cpuif.c | 4 ++++ > 1 file changed, 4 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index df82a413c6..afba98ad87 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -938,6 +938,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs) /* Tell the CPU about its highest priority pending interrupt */ int irqlevel = 0; int fiqlevel = 0; + int nmilevel = 0; ARMCPU *cpu = ARM_CPU(cs->cpu); CPUARMState *env = &cpu->env; @@ -976,6 +977,8 @@ void gicv3_cpuif_update(GICv3CPUState *cs) if (isfiq) { fiqlevel = 1; + } else if (cs->hppi.superprio) { + nmilevel = 1; } else { irqlevel = 1; } @@ -985,6 +988,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs) qemu_set_irq(cs->parent_fiq, fiqlevel); qemu_set_irq(cs->parent_irq, irqlevel); + qemu_set_irq(cs->parent_nmi, nmilevel); } static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
In CPU Interface, if the IRQ has the superpriority property, report NMI to the corresponding PE. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> --- v4: - Swap the ordering of the IFs. v3: - Remove handling nmi_is_irq flag. --- hw/intc/arm_gicv3_cpuif.c | 4 ++++ 1 file changed, 4 insertions(+)