| Message ID | 20240301145545.333810-2-liyongtai@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix unexpected Illegal instruction error on RISC-V. | expand |
Hi SiHuaN, On 1/3/24 15:55, SiHuaN wrote: > Avoid right-shifting by a negative number of bits when lmul is 8. FYI Demin posted a similar patch, see: https://lore.kernel.org/qemu-devel/20240225174114.5298-1-demin.han@starfivetech.com/ > Signed-off-by: SiHuaN <liyongtai@iscas.ac.cn> > --- > target/riscv/vector_helper.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 84cec73eb2..f0158ea237 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -53,10 +53,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > * VLEN * LMUL >= SEW > * VLEN >> (8 - lmul) >= sew > * (vlenb << 3) >> (8 - lmul) >= sew > + * Considering that lmul may be 8, the following form cannot be used. > * vlenb >> (8 - 3 - lmul) >= sew > */ > if (vlmul == 4 || > - cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) { > + (cpu->cfg.vlenb << 3) >> (8 - vlmul) < sew) { > vill = true; > } > }
Hi Philippe,
Thanks for the heads up. Sorry I didn't check for this before sending out my patch.
I'll track this in Demin's thread.
> -----原始邮件-----
> 发件人: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> 发送时间: 2024-03-01 23:51:03 (星期五)
> 收件人: SiHuaN <liyongtai@iscas.ac.cn>, qemu-devel@nongnu.org
> 抄送: "demin.han" <demin.han@starfivetech.com>, qemu-riscv <qemu-riscv@nongnu.org>, "Daniel Henrique Barboza" <dbarboza@ventanamicro.com>
> 主题: Re: [PATCH] Fix unexpected Illegal instruction error on RISC-V.
>
> Hi SiHuaN,
>
> On 1/3/24 15:55, SiHuaN wrote:
> > Avoid right-shifting by a negative number of bits when lmul is 8.
>
> FYI Demin posted a similar patch, see:
> https://lore.kernel.org/qemu-devel/20240225174114.5298-1-demin.han@starfivetech.com/
>
> > Signed-off-by: SiHuaN <liyongtai@iscas.ac.cn>
> > ---
> > target/riscv/vector_helper.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> > index 84cec73eb2..f0158ea237 100644
> > --- a/target/riscv/vector_helper.c
> > +++ b/target/riscv/vector_helper.c
> > @@ -53,10 +53,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> > * VLEN * LMUL >= SEW
> > * VLEN >> (8 - lmul) >= sew
> > * (vlenb << 3) >> (8 - lmul) >= sew
> > + * Considering that lmul may be 8, the following form cannot be used.
> > * vlenb >> (8 - 3 - lmul) >= sew
> > */
> > if (vlmul == 4 ||
> > - cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
> > + (cpu->cfg.vlenb << 3) >> (8 - vlmul) < sew) {
> > vill = true;
> > }
> > }
</liyongtai@iscas.ac.cn></dbarboza@ventanamicro.com></qemu-riscv@nongnu.org></demin.han@starfivetech.com></liyongtai@iscas.ac.cn></philmd@linaro.org>
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 84cec73eb2..f0158ea237 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -53,10 +53,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, * VLEN * LMUL >= SEW * VLEN >> (8 - lmul) >= sew * (vlenb << 3) >> (8 - lmul) >= sew + * Considering that lmul may be 8, the following form cannot be used. * vlenb >> (8 - 3 - lmul) >= sew */ if (vlmul == 4 || - cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) { + (cpu->cfg.vlenb << 3) >> (8 - vlmul) < sew) { vill = true; } }
Avoid right-shifting by a negative number of bits when lmul is 8. Signed-off-by: SiHuaN <liyongtai@iscas.ac.cn> --- target/riscv/vector_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)