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[5/5] target/riscv: Relax vector register check in RISCV gdbstub

Message ID 20240306170855.24341-6-jason.chien@sifive.com (mailing list archive)
State New, archived
Headers show
Series target/riscv: Support Zve32x and Zve64x extensions | expand

Commit Message

Jason Chien March 6, 2024, 5:08 p.m. UTC 
In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index ca9b71f7bb..f30de083e9 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -323,7 +323,7 @@  void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
         gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
                                  32, "riscv-32bit-fpu.xml", 0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         int base_reg = cs->gdb_num_regs;
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,