diff mbox series

[PULL,30/34] target/riscv: Fix shift count overflow

Message ID	20240308111152.2856137-31-alistair.francis@wdc.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, "demin.han" <demin.han@starfivetech.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 30/34] target/riscv: Fix shift count overflow Date: Fri, 8 Mar 2024 21:11:48 +1000 Message-ID: <20240308111152.2856137-31-alistair.francis@wdc.com> In-Reply-To: <20240308111152.2856137-1-alistair.francis@wdc.com> References: <20240308111152.2856137-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt() \| expand [PULL,01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt() [PULL,02/34] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location [PULL,03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table [PULL,04/34] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM [PULL,05/34] linux-user/riscv: Add Zicboz extensions to hwprobe [PULL,06/34] linux-user/riscv: Sync hwprobe keys with Linux [PULL,07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() [PULL,08/34] target/riscv: add riscv,isa to named features [PULL,09/34] target/riscv: add remaining named features [PULL,10/34] target/riscv: Reset henvcfg to zero [PULL,11/34] target/riscv: Gate hardware A/D PTE bit updating [PULL,12/34] target/riscv: Promote svade to a normal extension [PULL,13/34] target/riscv: FIX xATP_MODE validation [PULL,14/34] target/riscv: UPDATE xATP write CSR [PULL,15/34] target/riscv: Add missing include guard in pmu.h [PULL,16/34] hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables [PULL,17/34] hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier [PULL,18/34] hw/riscv/virt.c: add virtio-iommu-pci hotplug support [PULL,19/34] hw/riscv/virt.c: make aclint compatible with 'qtest' accel [PULL,20/34] tests/libqos: add riscv/virt machine nodes [PULL,21/34] RISC-V: Add support for Ztso [PULL,22/34] linux-user/riscv: Add Ztso extension to hwprobe [PULL,23/34] tests: riscv64: Use 'zfa' instead of 'Zfa' [PULL,24/34] linux-headers: Update to Linux v6.8-rc6 [PULL,25/34] target/riscv/kvm: update KVM exts to Linux 6.8 [PULL,26/34] target/riscv: move ratified/frozen exts to non-experimental [PULL,27/34] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit [PULL,28/34] trans_rvv.c.inc: mark_vs_dirty() before loads and stores [PULL,29/34] trans_rvv.c.inc: remove 'is_store' bool from load/store fns [PULL,30/34] target/riscv: Fix shift count overflow [PULL,31/34] hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode [PULL,32/34] hw/intc/riscv_aplic: Fix in_clrip[x] read emulation [PULL,33/34] target/riscv: Fix privilege mode of G-stage translation for debugging [PULL,34/34] target/riscv: fix ACPI MCFG table

Commit Message

Alistair Francis March 8, 2024, 11:11 a.m. UTC

From: "demin.han" <demin.han@starfivetech.com>

The result of (8 - 3 - vlmul) is negative when vlmul >= 6,
and results in wrong vill.

Signed-off-by: demin.han <demin.han@starfivetech.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff mbox series

Patch

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 84cec73eb2..fe56c007d5 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -44,6 +44,7 @@  target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     target_ulong reserved = s2 &
                             MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
                                             xlen - 1 - R_VTYPE_RESERVED_SHIFT);
+    uint16_t vlen = cpu->cfg.vlenb << 3;
     int8_t lmul;
 
     if (vlmul & 4) {
@@ -53,10 +54,8 @@  target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
          * VLEN * LMUL >= SEW
          * VLEN >> (8 - lmul) >= sew
          * (vlenb << 3) >> (8 - lmul) >= sew
-         * vlenb >> (8 - 3 - lmul) >= sew
          */
-        if (vlmul == 4 ||
-            cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
+        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
             vill = true;
         }
     }