| Message ID | 20240311185200.2185753-2-npiggin@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | misc ppc patches | expand |
On 3/12/24 00:21, Nicholas Piggin wrote: > The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of > any use in QEMU. Remove them. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- > hw/ppc/spapr_cpu_core.c | 2 -- > target/ppc/cpu-models.c | 4 ---- > target/ppc/cpu_init.c | 7 ++----- > target/ppc/kvm.c | 11 ----------- > 4 files changed, 2 insertions(+), 22 deletions(-) Do we want to squash in removal of the macro as well? diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0229ef3a9a..a5167873ae 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -348,7 +348,6 @@ enum { CPU_POWERPC_POWER8NVL_BASE = 0x004C0000, CPU_POWERPC_POWER8NVL_v10 = 0x004C0100, CPU_POWERPC_POWER9_BASE = 0x004E0000, - CPU_POWERPC_POWER9_DD1 = 0x004E1100, CPU_POWERPC_POWER9_DD20 = 0x004E1200, CPU_POWERPC_POWER9_DD22 = 0x004E1202, CPU_POWERPC_POWER10_BASE = 0x00800000, With that, Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> regards, Harsh > > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index 40b7c52f7f..50523ead25 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -394,10 +394,8 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { > DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), > DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), > - DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), > - DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), > #ifdef CONFIG_KVM > DEFINE_SPAPR_CPU_CORE_TYPE("host"), > diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c > index 36e465b390..f2301b43f7 100644 > --- a/target/ppc/cpu-models.c > +++ b/target/ppc/cpu-models.c > @@ -728,14 +728,10 @@ > "POWER8 v2.0") > POWERPC_DEF("power8nvl_v1.0", CPU_POWERPC_POWER8NVL_v10, POWER8, > "POWER8NVL v1.0") > - POWERPC_DEF("power9_v1.0", CPU_POWERPC_POWER9_DD1, POWER9, > - "POWER9 v1.0") > POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9, > "POWER9 v2.0") > POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9, > "POWER9 v2.2") > - POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10, > - "POWER10 v1.0") > POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, > "POWER10 v2.0") > #endif /* defined (TARGET_PPC64) */ > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 1d3d1db7c3..572cbdf25f 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6350,10 +6350,7 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > return false; > } > > - if ((pvr & 0x0f00) == 0x100) { > - /* DD1.x always matches power9_v1.0 */ > - return true; > - } else if ((pvr & 0x0f00) == 0x200) { > + if ((pvr & 0x0f00) == 0x200) { > if ((pvr & 0xf) < 2) { > /* DD2.0, DD2.1 match power9_v2.0 */ > if ((pcc->pvr & 0xf) == 0) { > @@ -6536,7 +6533,7 @@ static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > } > > if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { > - /* Major DD version matches to power10_v1.0 and power10_v2.0 */ > + /* Major DD version matches power10_v2.0 */ > return true; > } > > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c > index bcf30a5400..525fbe3892 100644 > --- a/target/ppc/kvm.c > +++ b/target/ppc/kvm.c > @@ -2369,17 +2369,6 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) > > #if defined(TARGET_PPC64) > pcc->radix_page_info = kvmppc_get_radix_page_info(); > - > - if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { > - /* > - * POWER9 DD1 has some bugs which make it not really ISA 3.00 > - * compliant. More importantly, advertising ISA 3.00 > - * architected mode may prevent guests from activating > - * necessary DD1 workarounds. > - */ > - pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 > - | PCR_COMPAT_2_06 | PCR_COMPAT_2_05); > - } > #endif /* defined(TARGET_PPC64) */ > } >
On 3/12/24 10:20, Harsh Prateek Bora wrote: > > > On 3/12/24 00:21, Nicholas Piggin wrote: >> The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of >> any use in QEMU. Remove them. >> >> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> >> --- >> hw/ppc/spapr_cpu_core.c | 2 -- >> target/ppc/cpu-models.c | 4 ---- >> target/ppc/cpu_init.c | 7 ++----- >> target/ppc/kvm.c | 11 ----------- >> 4 files changed, 2 insertions(+), 22 deletions(-) > > Do we want to squash in removal of the macro as well? > <snip> Actually both, correcting diff: diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0229ef3a9a..7d89b41214 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -348,11 +348,9 @@ enum { CPU_POWERPC_POWER8NVL_BASE = 0x004C0000, CPU_POWERPC_POWER8NVL_v10 = 0x004C0100, CPU_POWERPC_POWER9_BASE = 0x004E0000, - CPU_POWERPC_POWER9_DD1 = 0x004E1100, CPU_POWERPC_POWER9_DD20 = 0x004E1200, CPU_POWERPC_POWER9_DD22 = 0x004E1202, CPU_POWERPC_POWER10_BASE = 0x00800000, - CPU_POWERPC_POWER10_DD1 = 0x00801100, CPU_POWERPC_POWER10_DD20 = 0x00801200, CPU_POWERPC_970_v22 = 0x00390202, CPU_POWERPC_970FX_v10 = 0x00391100, > > With that, > > Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> > > regards, > Harsh > >> >> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c >> index 40b7c52f7f..50523ead25 100644 >> --- a/hw/ppc/spapr_cpu_core.c >> +++ b/hw/ppc/spapr_cpu_core.c >> @@ -394,10 +394,8 @@ static const TypeInfo spapr_cpu_core_type_infos[] >> = { >> DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), >> DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), >> DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), >> - DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), >> DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), >> DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), >> - DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), >> DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), >> #ifdef CONFIG_KVM >> DEFINE_SPAPR_CPU_CORE_TYPE("host"), >> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c >> index 36e465b390..f2301b43f7 100644 >> --- a/target/ppc/cpu-models.c >> +++ b/target/ppc/cpu-models.c >> @@ -728,14 +728,10 @@ >> "POWER8 v2.0") >> POWERPC_DEF("power8nvl_v1.0", CPU_POWERPC_POWER8NVL_v10, >> POWER8, >> "POWER8NVL v1.0") >> - POWERPC_DEF("power9_v1.0", CPU_POWERPC_POWER9_DD1, >> POWER9, >> - "POWER9 v1.0") >> POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, >> POWER9, >> "POWER9 v2.0") >> POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, >> POWER9, >> "POWER9 v2.2") >> - POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, >> POWER10, >> - "POWER10 v1.0") >> POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, >> POWER10, >> "POWER10 v2.0") >> #endif /* defined (TARGET_PPC64) */ >> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c >> index 1d3d1db7c3..572cbdf25f 100644 >> --- a/target/ppc/cpu_init.c >> +++ b/target/ppc/cpu_init.c >> @@ -6350,10 +6350,7 @@ static bool >> ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) >> return false; >> } >> - if ((pvr & 0x0f00) == 0x100) { >> - /* DD1.x always matches power9_v1.0 */ >> - return true; >> - } else if ((pvr & 0x0f00) == 0x200) { >> + if ((pvr & 0x0f00) == 0x200) { >> if ((pvr & 0xf) < 2) { >> /* DD2.0, DD2.1 match power9_v2.0 */ >> if ((pcc->pvr & 0xf) == 0) { >> @@ -6536,7 +6533,7 @@ static bool >> ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best) >> } >> if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { >> - /* Major DD version matches to power10_v1.0 and power10_v2.0 */ >> + /* Major DD version matches power10_v2.0 */ >> return true; >> } >> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c >> index bcf30a5400..525fbe3892 100644 >> --- a/target/ppc/kvm.c >> +++ b/target/ppc/kvm.c >> @@ -2369,17 +2369,6 @@ static void >> kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) >> #if defined(TARGET_PPC64) >> pcc->radix_page_info = kvmppc_get_radix_page_info(); >> - >> - if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { >> - /* >> - * POWER9 DD1 has some bugs which make it not really ISA 3.00 >> - * compliant. More importantly, advertising ISA 3.00 >> - * architected mode may prevent guests from activating >> - * necessary DD1 workarounds. >> - */ >> - pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 >> - | PCR_COMPAT_2_06 | PCR_COMPAT_2_05); >> - } >> #endif /* defined(TARGET_PPC64) */ >> } >
On Tue Mar 12, 2024 at 2:55 PM AEST, Harsh Prateek Bora wrote: > > > On 3/12/24 10:20, Harsh Prateek Bora wrote: > > > > > > On 3/12/24 00:21, Nicholas Piggin wrote: > >> The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of > >> any use in QEMU. Remove them. > >> > >> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > >> --- > >> hw/ppc/spapr_cpu_core.c | 2 -- > >> target/ppc/cpu-models.c | 4 ---- > >> target/ppc/cpu_init.c | 7 ++----- > >> target/ppc/kvm.c | 11 ----------- > >> 4 files changed, 2 insertions(+), 22 deletions(-) > > > > Do we want to squash in removal of the macro as well? > > > > <snip> > Actually both, correcting diff: > > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > index 0229ef3a9a..7d89b41214 100644 > --- a/target/ppc/cpu-models.h > +++ b/target/ppc/cpu-models.h > @@ -348,11 +348,9 @@ enum { > CPU_POWERPC_POWER8NVL_BASE = 0x004C0000, > CPU_POWERPC_POWER8NVL_v10 = 0x004C0100, > CPU_POWERPC_POWER9_BASE = 0x004E0000, > - CPU_POWERPC_POWER9_DD1 = 0x004E1100, > CPU_POWERPC_POWER9_DD20 = 0x004E1200, > CPU_POWERPC_POWER9_DD22 = 0x004E1202, > CPU_POWERPC_POWER10_BASE = 0x00800000, > - CPU_POWERPC_POWER10_DD1 = 0x00801100, > CPU_POWERPC_POWER10_DD20 = 0x00801200, > CPU_POWERPC_970_v22 = 0x00390202, > CPU_POWERPC_970FX_v10 = 0x00391100, That would make sense, but we do seem to use this list as somewhat of a reference or at least historic graveyard too (note all the other CPUs we no longer support). So I was going to just leave them there. Thanks, Nick
On 3/12/24 14:29, Nicholas Piggin wrote: > On Tue Mar 12, 2024 at 2:55 PM AEST, Harsh Prateek Bora wrote: >> >> >> On 3/12/24 10:20, Harsh Prateek Bora wrote: >>> >>> >>> On 3/12/24 00:21, Nicholas Piggin wrote: >>>> The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of >>>> any use in QEMU. Remove them. >>>> >>>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> >>>> --- >>>> hw/ppc/spapr_cpu_core.c | 2 -- >>>> target/ppc/cpu-models.c | 4 ---- >>>> target/ppc/cpu_init.c | 7 ++----- >>>> target/ppc/kvm.c | 11 ----------- >>>> 4 files changed, 2 insertions(+), 22 deletions(-) >>> >>> Do we want to squash in removal of the macro as well? >>> >> >> <snip> >> Actually both, correcting diff: >> >> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h >> index 0229ef3a9a..7d89b41214 100644 >> --- a/target/ppc/cpu-models.h >> +++ b/target/ppc/cpu-models.h >> @@ -348,11 +348,9 @@ enum { >> CPU_POWERPC_POWER8NVL_BASE = 0x004C0000, >> CPU_POWERPC_POWER8NVL_v10 = 0x004C0100, >> CPU_POWERPC_POWER9_BASE = 0x004E0000, >> - CPU_POWERPC_POWER9_DD1 = 0x004E1100, >> CPU_POWERPC_POWER9_DD20 = 0x004E1200, >> CPU_POWERPC_POWER9_DD22 = 0x004E1202, >> CPU_POWERPC_POWER10_BASE = 0x00800000, >> - CPU_POWERPC_POWER10_DD1 = 0x00801100, >> CPU_POWERPC_POWER10_DD20 = 0x00801200, >> CPU_POWERPC_970_v22 = 0x00390202, >> CPU_POWERPC_970FX_v10 = 0x00391100, > > That would make sense, but we do seem to use this list as somewhat of a > reference or at least historic graveyard too (note all the other CPUs we > no longer support). So I was going to just leave them there. Oh ok, in that case, it's fine. regards, Harsh > > Thanks, > Nick
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 40b7c52f7f..50523ead25 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -394,10 +394,8 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), - DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), - DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), #ifdef CONFIG_KVM DEFINE_SPAPR_CPU_CORE_TYPE("host"), diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index 36e465b390..f2301b43f7 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -728,14 +728,10 @@ "POWER8 v2.0") POWERPC_DEF("power8nvl_v1.0", CPU_POWERPC_POWER8NVL_v10, POWER8, "POWER8NVL v1.0") - POWERPC_DEF("power9_v1.0", CPU_POWERPC_POWER9_DD1, POWER9, - "POWER9 v1.0") POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9, "POWER9 v2.0") POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9, "POWER9 v2.2") - POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10, - "POWER10 v1.0") POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, "POWER10 v2.0") #endif /* defined (TARGET_PPC64) */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 1d3d1db7c3..572cbdf25f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6350,10 +6350,7 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) return false; } - if ((pvr & 0x0f00) == 0x100) { - /* DD1.x always matches power9_v1.0 */ - return true; - } else if ((pvr & 0x0f00) == 0x200) { + if ((pvr & 0x0f00) == 0x200) { if ((pvr & 0xf) < 2) { /* DD2.0, DD2.1 match power9_v2.0 */ if ((pcc->pvr & 0xf) == 0) { @@ -6536,7 +6533,7 @@ static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best) } if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { - /* Major DD version matches to power10_v1.0 and power10_v2.0 */ + /* Major DD version matches power10_v2.0 */ return true; } diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index bcf30a5400..525fbe3892 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2369,17 +2369,6 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) #if defined(TARGET_PPC64) pcc->radix_page_info = kvmppc_get_radix_page_info(); - - if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { - /* - * POWER9 DD1 has some bugs which make it not really ISA 3.00 - * compliant. More importantly, advertising ISA 3.00 - * architected mode may prevent guests from activating - * necessary DD1 workarounds. - */ - pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 - | PCR_COMPAT_2_06 | PCR_COMPAT_2_05); - } #endif /* defined(TARGET_PPC64) */ }
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- hw/ppc/spapr_cpu_core.c | 2 -- target/ppc/cpu-models.c | 4 ---- target/ppc/cpu_init.c | 7 ++----- target/ppc/kvm.c | 11 ----------- 4 files changed, 2 insertions(+), 22 deletions(-)