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Fri, 15 Mar 2024 06:11:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Markus Armbruster Cc: qemu-riscv@nongnu.org, Anton Johansson , qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, =?utf-8?q?Daniel_P_=2E_Berrang?= =?utf-8?q?=C3=A9?= , Paolo Bonzini , Eduardo Habkost , Claudio Fontana , Richard Henderson , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , Manos Pitsidianakis , Zhao Liu , qemu-arm@nongnu.org, Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [RFC PATCH-for-9.1 17/21] target/riscv: Use QMP generic_query_cpu_definitions() Date: Fri, 15 Mar 2024 14:09:05 +0100 Message-ID: <20240315130910.15750-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240315130910.15750-1-philmd@linaro.org> References: <20240315130910.15750-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Expose riscv_cpu_add_definition() and use it as add_definition() handler, then use the QMP generic_query_cpu_definitions() method. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 1 + target/riscv/riscv-qmp-cmds.c | 11 +++-------- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3b1a02b944..15fc287680 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -824,4 +824,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); uint8_t satp_mode_max_from_map(uint32_t map); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); +void riscv_cpu_add_definition(gpointer data, gpointer user_data); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c160b9216b..2da9364335 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2341,6 +2341,7 @@ static int64_t riscv_get_arch_id(CPUState *cs) #include "hw/core/sysemu-cpu-ops.h" static const struct SysemuCPUOps riscv_sysemu_ops = { + .add_definition = riscv_cpu_add_definition, .get_phys_page_debug = riscv_cpu_get_phys_page_debug, .write_elf64_note = riscv_cpu_write_elf64_note, .write_elf32_note = riscv_cpu_write_elf32_note, diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index d363dc318d..45adc90d3b 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qapi/qapi-commands-machine-target.h" +#include "qapi/commands-target-compat.h" #include "qapi/qmp/qbool.h" #include "qapi/qmp/qdict.h" #include "qapi/qobject-input-visitor.h" @@ -36,7 +37,7 @@ #include "cpu-qom.h" #include "cpu.h" -static void riscv_cpu_add_definition(gpointer data, gpointer user_data) +void riscv_cpu_add_definition(gpointer data, gpointer user_data) { ObjectClass *oc = data; CpuDefinitionInfoList **cpu_list = user_data; @@ -55,13 +56,7 @@ static void riscv_cpu_add_definition(gpointer data, gpointer user_data) CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) { - CpuDefinitionInfoList *cpu_list = NULL; - GSList *list = object_class_get_list(TYPE_RISCV_CPU, false); - - g_slist_foreach(list, riscv_cpu_add_definition, &cpu_list); - g_slist_free(list); - - return cpu_list; + return generic_query_cpu_definitions(errp); } static void riscv_check_if_cpu_available(RISCVCPU *cpu, Error **errp)