Message ID | 20240320083945.991426-31-michael.roth@amd.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Series |
Add AMD Secure Nested Paging (SEV-SNP) support
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expand
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 33760a2ee1..3fdaac3472 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6664,6 +6664,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (sev_enabled()) { *eax = 0x2; *eax |= sev_es_enabled() ? 0x8 : 0; + *eax |= sev_snp_enabled() ? 0x10 : 0; *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ }
SNP guests will rely on this bit to determine certain feature support. Signed-off-by: Michael Roth <michael.roth@amd.com> --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+)