diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 67e6b2effd..52ac667470 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2982,7 +2982,7 @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
 }
 #endif
 
-void dump_mmu(CPUPPCState *env);
+void ppc_dump_mmu(Monitor *mon, CPUPPCState *env);
 
 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
 void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 751403f1c8..ba8e91b949 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -32,6 +32,7 @@
 #include "internal.h"
 #include "mmu-book3s-v3.h"
 #include "mmu-radix64.h"
+#include "monitor/monitor.h"
 
 /* #define DUMP_PAGE_TABLES */
 
@@ -924,21 +925,21 @@ static const char *book3e_tsize_to_str[32] = {
     "1T", "2T"
 };
 
-static void mmubooke_dump_mmu(CPUPPCState *env)
+static void mmubooke_dump_mmu(Monitor *mon, CPUPPCState *env)
 {
     ppcemb_tlb_t *entry;
     int i;
 
 #ifdef CONFIG_KVM
     if (kvm_enabled() && !env->kvm_sw_tlb) {
-        qemu_printf("Cannot access KVM TLB\n");
+        monitor_puts(mon, "Cannot access KVM TLB\n");
         return;
     }
 #endif
 
-    qemu_printf("\nTLB:\n");
-    qemu_printf("Effective          Physical           Size PID   Prot     "
-                "Attr\n");
+    monitor_puts(mon, "\nTLB:\n");
+    monitor_puts(mon, "Effective          Physical           Size PID   Prot     "
+                 "Attr\n");
 
     entry = &env->tlb.tlbe[0];
     for (i = 0; i < env->nb_tlb; i++, entry++) {
@@ -962,22 +963,22 @@ static void mmubooke_dump_mmu(CPUPPCState *env)
         } else {
             snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "k", size / KiB);
         }
-        qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n",
-                    (uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID,
-                    entry->prot, entry->attr);
+        monitor_printf(mon, "0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n",
+                       (uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID,
+                       entry->prot, entry->attr);
     }
 
 }
 
-static void mmubooke206_dump_one_tlb(CPUPPCState *env, int tlbn, int offset,
-                                     int tlbsize)
+static void mmubooke206_dump_one_tlb(Monitor *mon, CPUPPCState *env,
+                                     int tlbn, int offset, int tlbsize)
 {
     ppcmas_tlb_t *entry;
     int i;
 
-    qemu_printf("\nTLB%d:\n", tlbn);
-    qemu_printf("Effective          Physical           Size TID   TS SRWX"
-                " URWX WIMGE U0123\n");
+    monitor_printf(mon, "\nTLB%d:\n", tlbn);
+    monitor_puts(mon, "Effective          Physical           Size TID   TS SRWX"
+                 " URWX WIMGE U0123\n");
 
     entry = &env->tlb.tlbm[offset];
     for (i = 0; i < tlbsize; i++, entry++) {
@@ -993,38 +994,38 @@ static void mmubooke206_dump_one_tlb(CPUPPCState *env, int tlbn, int offset,
         ea = entry->mas2 & ~(size - 1);
         pa = entry->mas7_3 & ~(size - 1);
 
-        qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u  S%c%c%c"
-                    " U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
-                    (uint64_t)ea, (uint64_t)pa,
-                    book3e_tsize_to_str[tsize],
-                    (entry->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT,
-                    (entry->mas1 & MAS1_TS) >> MAS1_TS_SHIFT,
-                    entry->mas7_3 & MAS3_SR ? 'R' : '-',
-                    entry->mas7_3 & MAS3_SW ? 'W' : '-',
-                    entry->mas7_3 & MAS3_SX ? 'X' : '-',
-                    entry->mas7_3 & MAS3_UR ? 'R' : '-',
-                    entry->mas7_3 & MAS3_UW ? 'W' : '-',
-                    entry->mas7_3 & MAS3_UX ? 'X' : '-',
-                    entry->mas2 & MAS2_W ? 'W' : '-',
-                    entry->mas2 & MAS2_I ? 'I' : '-',
-                    entry->mas2 & MAS2_M ? 'M' : '-',
-                    entry->mas2 & MAS2_G ? 'G' : '-',
-                    entry->mas2 & MAS2_E ? 'E' : '-',
-                    entry->mas7_3 & MAS3_U0 ? '0' : '-',
-                    entry->mas7_3 & MAS3_U1 ? '1' : '-',
-                    entry->mas7_3 & MAS3_U2 ? '2' : '-',
-                    entry->mas7_3 & MAS3_U3 ? '3' : '-');
+        monitor_printf(mon, "0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u  S%c%c%c"
+                       " U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
+                       (uint64_t)ea, (uint64_t)pa,
+                       book3e_tsize_to_str[tsize],
+                       (entry->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT,
+                       (entry->mas1 & MAS1_TS) >> MAS1_TS_SHIFT,
+                       entry->mas7_3 & MAS3_SR ? 'R' : '-',
+                       entry->mas7_3 & MAS3_SW ? 'W' : '-',
+                       entry->mas7_3 & MAS3_SX ? 'X' : '-',
+                       entry->mas7_3 & MAS3_UR ? 'R' : '-',
+                       entry->mas7_3 & MAS3_UW ? 'W' : '-',
+                       entry->mas7_3 & MAS3_UX ? 'X' : '-',
+                       entry->mas2 & MAS2_W ? 'W' : '-',
+                       entry->mas2 & MAS2_I ? 'I' : '-',
+                       entry->mas2 & MAS2_M ? 'M' : '-',
+                       entry->mas2 & MAS2_G ? 'G' : '-',
+                       entry->mas2 & MAS2_E ? 'E' : '-',
+                       entry->mas7_3 & MAS3_U0 ? '0' : '-',
+                       entry->mas7_3 & MAS3_U1 ? '1' : '-',
+                       entry->mas7_3 & MAS3_U2 ? '2' : '-',
+                       entry->mas7_3 & MAS3_U3 ? '3' : '-');
     }
 }
 
-static void mmubooke206_dump_mmu(CPUPPCState *env)
+static void mmubooke206_dump_mmu(Monitor *mon, CPUPPCState *env)
 {
     int offset = 0;
     int i;
 
 #ifdef CONFIG_KVM
     if (kvm_enabled() && !env->kvm_sw_tlb) {
-        qemu_printf("Cannot access KVM TLB\n");
+        monitor_puts(mon, "Cannot access KVM TLB\n");
         return;
     }
 #endif
@@ -1036,12 +1037,12 @@ static void mmubooke206_dump_mmu(CPUPPCState *env)
             continue;
         }
 
-        mmubooke206_dump_one_tlb(env, i, offset, size);
+        mmubooke206_dump_one_tlb(mon, env, i, offset, size);
         offset += size;
     }
 }
 
-static void mmu6xx_dump_BATs(CPUPPCState *env, int type)
+static void mmu6xx_dump_BATs(Monitor *mon, CPUPPCState *env, int type)
 {
     target_ulong *BATlt, *BATut, *BATu, *BATl;
     target_ulong BEPIl, BEPIu, bl;
@@ -1064,51 +1065,53 @@ static void mmu6xx_dump_BATs(CPUPPCState *env, int type)
         BEPIu = *BATu & 0xF0000000;
         BEPIl = *BATu & 0x0FFE0000;
         bl = (*BATu & 0x00001FFC) << 15;
-        qemu_printf("%s BAT%d BATu " TARGET_FMT_lx
-                    " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
-                    TARGET_FMT_lx " " TARGET_FMT_lx "\n",
-                    type == ACCESS_CODE ? "code" : "data", i,
-                    *BATu, *BATl, BEPIu, BEPIl, bl);
+        monitor_printf(mon, "%s BAT%d BATu " TARGET_FMT_lx
+                       " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
+                       TARGET_FMT_lx " " TARGET_FMT_lx "\n",
+                       type == ACCESS_CODE ? "code" : "data", i,
+                       *BATu, *BATl, BEPIu, BEPIl, bl);
     }
 }
 
-static void mmu6xx_dump_mmu(CPUPPCState *env)
+static void mmu6xx_dump_mmu(Monitor *mon, CPUPPCState *env)
 {
     PowerPCCPU *cpu = env_archcpu(env);
     ppc6xx_tlb_t *tlb;
     target_ulong sr;
     int type, way, entry, i;
 
-    qemu_printf("HTAB base = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(cpu));
-    qemu_printf("HTAB mask = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(cpu));
+    monitor_printf(mon, "HTAB base = 0x%"HWADDR_PRIx"\n",
+                   ppc_hash32_hpt_base(cpu));
+    monitor_printf(mon, "HTAB mask = 0x%"HWADDR_PRIx"\n",
+                   ppc_hash32_hpt_mask(cpu));
 
-    qemu_printf("\nSegment registers:\n");
+    monitor_puts(mon, "\nSegment registers:\n");
     for (i = 0; i < 32; i++) {
         sr = env->sr[i];
         if (sr & 0x80000000) {
-            qemu_printf("%02d T=%d Ks=%d Kp=%d BUID=0x%03x "
-                        "CNTLR_SPEC=0x%05x\n", i,
-                        sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
-                        sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF),
-                        (uint32_t)(sr & 0xFFFFF));
+            monitor_printf(mon, "%02d T=%d Ks=%d Kp=%d BUID=0x%03x "
+                           "CNTLR_SPEC=0x%05x\n", i,
+                           sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
+                           sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF),
+                           (uint32_t)(sr & 0xFFFFF));
         } else {
-            qemu_printf("%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i,
-                        sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
-                        sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0,
-                        (uint32_t)(sr & 0x00FFFFFF));
+            monitor_printf(mon, "%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i,
+                           sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
+                           sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0,
+                           (uint32_t)(sr & 0x00FFFFFF));
         }
     }
 
-    qemu_printf("\nBATs:\n");
-    mmu6xx_dump_BATs(env, ACCESS_INT);
-    mmu6xx_dump_BATs(env, ACCESS_CODE);
+    monitor_puts(mon, "\nBATs:\n");
+    mmu6xx_dump_BATs(mon, env, ACCESS_INT);
+    mmu6xx_dump_BATs(mon, env, ACCESS_CODE);
 
     if (env->id_tlbs != 1) {
-        qemu_printf("ERROR: 6xx MMU should have separated TLB"
-                    " for code and data\n");
+        monitor_puts(mon, "ERROR: 6xx MMU should have separated TLB"
+                     " for code and data\n");
     }
 
-    qemu_printf("\nTLBs                       [EPN    EPN + SIZE]\n");
+    monitor_puts(mon, "\nTLBs                       [EPN    EPN + SIZE]\n");
 
     for (type = 0; type < 2; type++) {
         for (way = 0; way < env->nb_ways; way++) {
@@ -1117,28 +1120,28 @@ static void mmu6xx_dump_mmu(CPUPPCState *env)
                  entry++) {
 
                 tlb = &env->tlb.tlb6[entry];
-                qemu_printf("%s TLB %02d/%02d way:%d %s ["
-                            TARGET_FMT_lx " " TARGET_FMT_lx "]\n",
-                            type ? "code" : "data", entry % env->nb_tlb,
-                            env->nb_tlb, way,
-                            pte_is_valid(tlb->pte0) ? "valid" : "inval",
-                            tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE);
+                monitor_printf(mon, "%s TLB %02d/%02d way:%d %s ["
+                               TARGET_FMT_lx " " TARGET_FMT_lx "]\n",
+                               type ? "code" : "data", entry % env->nb_tlb,
+                               env->nb_tlb, way,
+                               pte_is_valid(tlb->pte0) ? "valid" : "inval",
+                               tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE);
             }
         }
     }
 }
 
-void dump_mmu(CPUPPCState *env)
+void ppc_dump_mmu(Monitor *mon, CPUPPCState *env)
 {
     switch (env->mmu_model) {
     case POWERPC_MMU_BOOKE:
-        mmubooke_dump_mmu(env);
+        mmubooke_dump_mmu(mon, env);
         break;
     case POWERPC_MMU_BOOKE206:
-        mmubooke206_dump_mmu(env);
+        mmubooke206_dump_mmu(mon, env);
         break;
     case POWERPC_MMU_SOFT_6xx:
-        mmu6xx_dump_mmu(env);
+        mmu6xx_dump_mmu(mon, env);
         break;
 #if defined(TARGET_PPC64)
     case POWERPC_MMU_64B:
diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c
index a25d86a8d1..e798c30f91 100644
--- a/target/ppc/ppc-qmp-cmds.c
+++ b/target/ppc/ppc-qmp-cmds.c
@@ -88,7 +88,7 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
         monitor_printf(mon, "No CPU available\n");
         return;
     }
-    dump_mmu(env1);
+    ppc_dump_mmu(mon, env1);
 }
 
 const MonitorDef monitor_defs[] = {
