| Message ID | 20240409164323.776660-11-pbonzini@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/i386: convert 1-byte opcodes to new decoder | expand |
On 4/9/24 06:43, Paolo Bonzini wrote: > In the new decoder it is sometimes easier to put the segment > in T1 instead of T0, usually because another operand was loaded > by common code in T0. Genrealize gen_movl_seg_T0 to allow > using any source. > > Signed-off-by: Paolo Bonzini<pbonzini@redhat.com> > --- > target/i386/tcg/translate.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
Hi Paolo, On Tue, Apr 09, 2024 at 06:43:14PM +0200, Paolo Bonzini wrote: > Date: Tue, 9 Apr 2024 18:43:14 +0200 > From: Paolo Bonzini <pbonzini@redhat.com> > Subject: [PATCH for-9.1 10/19] target/i386: generalize gen_movl_seg_T0 > X-Mailer: git-send-email 2.44.0 > > In the new decoder it is sometimes easier to put the segment > in T1 instead of T0, usually because another operand was loaded > by common code in T0. Genrealize gen_movl_seg_T0 to allow > using any source. > > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > --- > target/i386/tcg/translate.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c > index de1ccb6ea7f..8a34e50c452 100644 > --- a/target/i386/tcg/translate.c > +++ b/target/i386/tcg/translate.c > @@ -2531,12 +2531,12 @@ static void gen_op_movl_seg_real(DisasContext *s, X86Seg seg_reg, TCGv seg) > tcg_gen_shli_tl(cpu_seg_base[seg_reg], selector, 4); > } > > -/* move T0 to seg_reg and compute if the CPU state may change. Never > +/* move SRC to seg_reg and compute if the CPU state may change. Never > call this function with seg_reg == R_CS */ > -static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) > +static void gen_movl_seg(DisasContext *s, X86Seg seg_reg, TCGv src) > { > if (PE(s) && !VM86(s)) { > - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); > + tcg_gen_trunc_tl_i32(s->tmp2_i32, src); > gen_helper_load_seg(tcg_env, tcg_constant_i32(seg_reg), s->tmp2_i32); > /* abort translation because the addseg value may change or > because ss32 may change. For R_SS, translation must always This patch missed to include another gen_movl_seg_T0() use in emit.c.inc, which was cleaned up later in patch 11. We could move that cleanup into this patch to avoid compiling failures. -Zhao
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index de1ccb6ea7f..8a34e50c452 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2531,12 +2531,12 @@ static void gen_op_movl_seg_real(DisasContext *s, X86Seg seg_reg, TCGv seg) tcg_gen_shli_tl(cpu_seg_base[seg_reg], selector, 4); } -/* move T0 to seg_reg and compute if the CPU state may change. Never +/* move SRC to seg_reg and compute if the CPU state may change. Never call this function with seg_reg == R_CS */ -static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) +static void gen_movl_seg(DisasContext *s, X86Seg seg_reg, TCGv src) { if (PE(s) && !VM86(s)) { - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); + tcg_gen_trunc_tl_i32(s->tmp2_i32, src); gen_helper_load_seg(tcg_env, tcg_constant_i32(seg_reg), s->tmp2_i32); /* abort translation because the addseg value may change or because ss32 may change. For R_SS, translation must always @@ -2548,7 +2548,7 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) s->base.is_jmp = DISAS_EOB_NEXT; } } else { - gen_op_movl_seg_real(s, seg_reg, s->T0); + gen_op_movl_seg_real(s, seg_reg, src); if (seg_reg == R_SS) { s->base.is_jmp = DISAS_EOB_INHIBIT_IRQ; } @@ -4086,13 +4086,13 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; reg = b >> 3; ot = gen_pop_T0(s); - gen_movl_seg_T0(s, reg); + gen_movl_seg(s, reg, s->T0); gen_pop_update(s, ot); break; case 0x1a1: /* pop fs */ case 0x1a9: /* pop gs */ ot = gen_pop_T0(s); - gen_movl_seg_T0(s, (b >> 3) & 7); + gen_movl_seg(s, (b >> 3) & 7, s->T0); gen_pop_update(s, ot); break; @@ -4139,7 +4139,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (reg >= 6 || reg == R_CS) goto illegal_op; gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); - gen_movl_seg_T0(s, reg); + gen_movl_seg(s, reg, s->T0); break; case 0x8c: /* mov Gv, seg */ modrm = x86_ldub_code(env, s); @@ -4325,7 +4325,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_add_A0_im(s, 1 << ot); /* load the segment first to handle exceptions properly */ gen_op_ld_v(s, MO_16, s->T0, s->A0); - gen_movl_seg_T0(s, op); + gen_movl_seg(s, op, s->T0); /* then put the data */ gen_op_mov_reg_v(s, ot, reg, s->T1); break;
In the new decoder it is sometimes easier to put the segment in T1 instead of T0, usually because another operand was loaded by common code in T0. Genrealize gen_movl_seg_T0 to allow using any source. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- target/i386/tcg/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)