| Message ID | 20240416230437.1869024-3-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: set tval in breakpoints | expand |
On 4/16/24 16:04, Daniel Henrique Barboza wrote: > Privileged spec section 4.1.9 mentions: > > "When a trap is taken into S-mode, stval is written with > exception-specific information to assist software in handling the trap. > (...) > > If stval is written with a nonzero value when a breakpoint, > address-misaligned, access-fault, or page-fault exception occurs on an > instruction fetch, load, or store, then stval will contain the faulting > virtual address." > > A similar text is found for mtval in section 3.1.16. > > Setting mtval/stval in this scenario is optional, but some softwares read > these regs when handling ebreaks. > > Write 'badaddr' in all ebreak breakpoints to write the appropriate > 'tval' during riscv_do_cpu_interrrupt(). > > Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com> > --- > target/riscv/insn_trans/trans_privileged.c.inc | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 2024/4/17 7:04, Daniel Henrique Barboza wrote: > Privileged spec section 4.1.9 mentions: > > "When a trap is taken into S-mode, stval is written with > exception-specific information to assist software in handling the trap. > (...) > > If stval is written with a nonzero value when a breakpoint, > address-misaligned, access-fault, or page-fault exception occurs on an > instruction fetch, load, or store, then stval will contain the faulting > virtual address." > > A similar text is found for mtval in section 3.1.16. > > Setting mtval/stval in this scenario is optional, but some softwares read > these regs when handling ebreaks. > > Write 'badaddr' in all ebreak breakpoints to write the appropriate > 'tval' during riscv_do_cpu_interrrupt(). > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/insn_trans/trans_privileged.c.inc | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc > index 620ab54eb0..bc5263a4e0 100644 > --- a/target/riscv/insn_trans/trans_privileged.c.inc > +++ b/target/riscv/insn_trans/trans_privileged.c.inc > @@ -62,6 +62,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) > if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { > generate_exception(ctx, RISCV_EXCP_SEMIHOST); > } else { > + tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env, > + offsetof(CPURISCVState, badaddr)); Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > generate_exception(ctx, RISCV_EXCP_BREAKPOINT); > } > return true;
On Wed, Apr 17, 2024 at 9:05 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Privileged spec section 4.1.9 mentions: > > "When a trap is taken into S-mode, stval is written with > exception-specific information to assist software in handling the trap. > (...) > > If stval is written with a nonzero value when a breakpoint, > address-misaligned, access-fault, or page-fault exception occurs on an > instruction fetch, load, or store, then stval will contain the faulting > virtual address." > > A similar text is found for mtval in section 3.1.16. > > Setting mtval/stval in this scenario is optional, but some softwares read > these regs when handling ebreaks. > > Write 'badaddr' in all ebreak breakpoints to write the appropriate > 'tval' during riscv_do_cpu_interrrupt(). > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_privileged.c.inc | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc > index 620ab54eb0..bc5263a4e0 100644 > --- a/target/riscv/insn_trans/trans_privileged.c.inc > +++ b/target/riscv/insn_trans/trans_privileged.c.inc > @@ -62,6 +62,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) > if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { > generate_exception(ctx, RISCV_EXCP_SEMIHOST); > } else { > + tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env, > + offsetof(CPURISCVState, badaddr)); > generate_exception(ctx, RISCV_EXCP_BREAKPOINT); > } > return true; > -- > 2.44.0 > >
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 620ab54eb0..bc5263a4e0 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -62,6 +62,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { generate_exception(ctx, RISCV_EXCP_SEMIHOST); } else { + tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env, + offsetof(CPURISCVState, badaddr)); generate_exception(ctx, RISCV_EXCP_BREAKPOINT); } return true;
Privileged spec section 4.1.9 mentions: "When a trap is taken into S-mode, stval is written with exception-specific information to assist software in handling the trap. (...) If stval is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then stval will contain the faulting virtual address." A similar text is found for mtval in section 3.1.16. Setting mtval/stval in this scenario is optional, but some softwares read these regs when handling ebreaks. Write 'badaddr' in all ebreak breakpoints to write the appropriate 'tval' during riscv_do_cpu_interrrupt(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/insn_trans/trans_privileged.c.inc | 2 ++ 1 file changed, 2 insertions(+)