| Message ID | 20240418133916.1442471-2-cleger@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Add support for Smdbltrp and Ssdbltrp extensions | expand |
On Thu, Apr 18, 2024 at 11:40 PM Clément Léger <cleger@rivosinc.com> wrote: > > The double trap specification defines the double trap exception number > to be 16 which is actually used by the internal semihosting one. Change > it to some other value. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_bits.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index fc2068ee4d..9ade72ff31 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -670,7 +670,7 @@ typedef enum RISCVException { > RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ > RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ > RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ > - RISCV_EXCP_SEMIHOST = 0x10, > + RISCV_EXCP_SEMIHOST = 0x11, > RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, > RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, > RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, > -- > 2.43.0 > >
On 22/04/2024 05:25, Alistair Francis wrote: > On Thu, Apr 18, 2024 at 11:40 PM Clément Léger <cleger@rivosinc.com> wrote: >> >> The double trap specification defines the double trap exception number >> to be 16 which is actually used by the internal semihosting one. Change >> it to some other value. >> >> Signed-off-by: Clément Léger <cleger@rivosinc.com> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Hi Alistair, Ved actually told me that even 17 is reserved so I'll move the semihost one to 63, which is in a range designated for custom use. Regards, Clément > > Alistair > >> --- >> target/riscv/cpu_bits.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index fc2068ee4d..9ade72ff31 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -670,7 +670,7 @@ typedef enum RISCVException { >> RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ >> RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ >> RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ >> - RISCV_EXCP_SEMIHOST = 0x10, >> + RISCV_EXCP_SEMIHOST = 0x11, >> RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, >> RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, >> RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, >> -- >> 2.43.0 >> >>
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fc2068ee4d..9ade72ff31 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -670,7 +670,7 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ - RISCV_EXCP_SEMIHOST = 0x10, + RISCV_EXCP_SEMIHOST = 0x11, RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
The double trap specification defines the double trap exception number to be 16 which is actually used by the internal semihosting one. Change it to some other value. Signed-off-by: Clément Léger <cleger@rivosinc.com> --- target/riscv/cpu_bits.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)