From patchwork Wed Apr 24 15:49:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13642093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D547BC4345F for ; Wed, 24 Apr 2024 15:38:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzegV-0005tJ-P1; Wed, 24 Apr 2024 11:37:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzegR-0005Mp-Bi for qemu-devel@nongnu.org; Wed, 24 Apr 2024 11:37:19 -0400 Received: from mgamail.intel.com ([192.198.163.13]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzegO-0005hB-TP for qemu-devel@nongnu.org; Wed, 24 Apr 2024 11:37:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713973037; x=1745509037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iIl0C+Qixsw04e7TkAPrjhJFuOEqzJHHadMylFCGKCE=; b=FAHwgCFsXbVBqXSoSI90iV6LUFZ/zC3d77+mmsQIyfzFH8T35tD7oGbZ 3tbdX04qyZkNCb8bhXDO/8/cYZcwVYAGtVzcd5lpBfdH7A9I6bzn6wc1k OzpwDrCxB+umeLPeGxthIB+K//mZ8l0JWNTiJtMfOo0NlpHtjKoVZ1mMA pvbkgUHTFpYtGOFK2RF+V2+53mZDSat7WjVLMZ2tMhyBO/qClPv3qLX1F AlEGIs/U1w3vtsudW1nhgZ6zkGpMO0+hnIiuUb8awt9EWJY1thb4eyNlM CQgYqGRucYcPWvVVLNoDVx0Hem00p2hG2WI82i3QK5e9NF59YJfcNUwi8 A==; X-CSE-ConnectionGUID: 1wgao5VLTem2623JbfOkeQ== X-CSE-MsgGUID: eqmr7WQrQx6wx9sT9zJ2qw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="12545787" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="12545787" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 08:37:06 -0700 X-CSE-ConnectionGUID: aXTSxeZKTUG/WEVDwsyX1g== X-CSE-MsgGUID: 0d3aahLiQzKh1p3y71cYXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="25363317" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa008.jf.intel.com with ESMTP; 24 Apr 2024 08:37:02 -0700 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Xiaoyao Li , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH v11 14/21] i386: Expose module level in CPUID[0x1F] Date: Wed, 24 Apr 2024 23:49:22 +0800 Message-Id: <20240424154929.1487382-15-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424154929.1487382-1-zhao1.liu@intel.com> References: <20240424154929.1487382-1-zhao1.liu@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.198.163.13; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -50 X-Spam_score: -5.1 X-Spam_bar: ----- X-Spam_report: (-5.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.668, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix erroneous smp_num_siblings on Intel Hybrid platforms") is able to handle platforms with Module level enumerated via CPUID.1F. Expose the module level in CPUID[0x1F] if the machine has more than 1 modules. Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Tested-by: Babu Moger --- Changes since v7: * Mapped x86 module to smp module instead of cluster. * Dropped Michael/Babu's ACKed/Tested tags since the code change. * Re-added Yongwei's Tested tag For his re-testing. Changes since v3: * New patch to expose module level in 0x1F. * Added Tested-by tag from Yongwei. --- hw/i386/x86.c | 2 +- include/hw/i386/topology.h | 6 ++++-- target/i386/cpu.c | 6 ++++++ target/i386/cpu.h | 1 + 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index f2a0f68020d6..69f56aafeed6 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -322,7 +322,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, if (ms->smp.modules > 1) { env->nr_modules = ms->smp.modules; - /* TODO: Expose module level in CPUID[0x1F]. */ + set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo); } if (ms->smp.dies > 1) { diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 7622d806932c..ea871045779d 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -71,6 +71,7 @@ enum CPUTopoLevel { CPU_TOPO_LEVEL_INVALID, CPU_TOPO_LEVEL_SMT, CPU_TOPO_LEVEL_CORE, + CPU_TOPO_LEVEL_MODULE, CPU_TOPO_LEVEL_DIE, CPU_TOPO_LEVEL_PACKAGE, CPU_TOPO_LEVEL_MAX, @@ -198,11 +199,12 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info, } /* - * Check whether there's extended topology level (die)? + * Check whether there's extended topology level (module or die)? */ static inline bool x86_has_extended_topo(unsigned long *topo_bitmap) { - return test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap); + return test_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap) || + test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap); } #endif /* HW_I386_TOPOLOGY_H */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5c6936dd0253..a637a8ad8f51 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -277,6 +277,8 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, return 1; case CPU_TOPO_LEVEL_CORE: return topo_info->threads_per_core; + case CPU_TOPO_LEVEL_MODULE: + return topo_info->threads_per_core * topo_info->cores_per_module; case CPU_TOPO_LEVEL_DIE: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die; @@ -297,6 +299,8 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, return 0; case CPU_TOPO_LEVEL_CORE: return apicid_core_offset(topo_info); + case CPU_TOPO_LEVEL_MODULE: + return apicid_module_offset(topo_info); case CPU_TOPO_LEVEL_DIE: return apicid_die_offset(topo_info); case CPU_TOPO_LEVEL_PACKAGE: @@ -316,6 +320,8 @@ static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) return CPUID_1F_ECX_TOPO_LEVEL_SMT; case CPU_TOPO_LEVEL_CORE: return CPUID_1F_ECX_TOPO_LEVEL_CORE; + case CPU_TOPO_LEVEL_MODULE: + return CPUID_1F_ECX_TOPO_LEVEL_MODULE; case CPU_TOPO_LEVEL_DIE: return CPUID_1F_ECX_TOPO_LEVEL_DIE; default: diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 630129838c08..b0ecf90460ab 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1025,6 +1025,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID #define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT #define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE +#define CPUID_1F_ECX_TOPO_LEVEL_MODULE 3 #define CPUID_1F_ECX_TOPO_LEVEL_DIE 5 /* MSR Feature Bits */